From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECEBDC25B74 for ; Thu, 16 May 2024 11:38:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KXeCzGQYI21SPqkODj4WHH/wXvGedXZ9ax/TyGb55As=; b=vckmSeyGE/KKCm tMWS6ydyhRDm6bSa/LPVTXvxvDMXfxvn/TJsd+LM1ScLAhfFXpLJEsOlS1ZILGogz6ozFmjSVhK5E IofiFm4LjCwh2WkRljblzdkqFDJtNmS3MCvjil2ARq6A8mDmTkp2IdT6gUYujrssOULm7tEOHHZ8O FdKuOsxpMdwgOrc1ze8zMee2Bo9FjWJRkWbCIOwmhzUe9rp52votj7rf20/R7MB+Fm3kGblQplW/r K2RcjDR+9T1/yLqueBC0wgtwSlID3o4IvjjT+YEQknM2/mEEGBAJZWdSDYQ5OyvtHjG+9yXi0rK5Q Yi9SPMkSI2NcJrBbyJVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7ZRa-00000004e6T-2Bgy; Thu, 16 May 2024 11:38:42 +0000 Received: from madrid.collaboradmins.com ([2a00:1098:ed:100::25]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7ZRX-00000004e5x-3feU for linux-arm-kernel@lists.infradead.org; Thu, 16 May 2024 11:38:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1715859513; bh=6YlANbTSJp+DD89N4n3iOkjqTuHNDTJa4CMV9yVdZkM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=EnW+unrUCcxibLwEbfR1jJVHOgS3THUQZzkyGgnVBV2r8SX3rWjQ5hjDbDaeep5uc nuO/SOHzZ1g3XKmounte9suRLuquEUfoX+mMZRKKFv7f0VP4kr/Ui4UW9IWOmD/NxH 3s4rqZlKExzQ+vTdC0ZprCl1JgIvBCzcZCLC1g54BtTzekmkqKNI5cwMBx1RSuv4Rw s1Nmb0phK8jnffAlbg3Yi0rslYT8Twphh1cbYANvEZt3avsIhFYESj6Xy5isK4Mj/w W6H2PQUVjYCAyLFajFQi3vQc4eKFfYV8SWdTfk/fVSBBdCHq8EZVwTf9d27ZKMRvEG h9lOwBaTP0knA== Received: from [100.113.186.2] (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 898683782186; Thu, 16 May 2024 11:38:32 +0000 (UTC) Message-ID: Date: Thu, 16 May 2024 13:38:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC. To: Lorenzo Bianconi Cc: linux-clk@vger.kernel.org, p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com References: From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240516_043840_126867_20AA5ADE X-CRM114-Status: GOOD ( 14.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Il 16/05/24 13:14, Lorenzo Bianconi ha scritto: >> Il 15/05/24 14:58, Lorenzo Bianconi ha scritto: >>> Introduce reset binding definitions for reset controller available in >>> the Airoha EN7581 clock module. >>> >>> Tested-by: Zhengping Zhang >>> Signed-off-by: Lorenzo Bianconi >>> --- >>> .../dt-bindings/reset/airoha,en7581-reset.h | 66 +++++++++++++++++++ >>> 1 file changed, 66 insertions(+) >>> create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h >>> >>> diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h >>> new file mode 100644 >>> index 000000000000..1b7ee62ed164 >>> --- /dev/null >>> +++ b/include/dt-bindings/reset/airoha,en7581-reset.h >>> @@ -0,0 +1,66 @@ >>> +// SPDX-License-Identifier: GPL-2.0-only >>> +/* >>> + * Copyright (c) 2024 AIROHA Inc >>> + * Author: Lorenzo Bianconi >>> + */ >>> + >>> +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ >>> +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ >>> + >>> +/* RST_CTRL2 */ >>> +#define EN7581_XPON_PHY_RST 0 >> >> ** sarcasm mode on ** >> >> Count with me: 0... 1... 2... > > :) > >> >> ** sarcasm mode off ** >> >> There's a jump here, you have a reset index 0 and an index 2, >> but you're missing index 1, that's not right :-) >> >> Please fix. > > it is because BIT(1) is marked as 'reserved' in the documentation so I skipped it. > Do you prefer to have it in that way? > This is not my preference, it's rather a requirement for the bindings... That's why in the MediaTek reset controller part of the clk driver there is a way to map those numbers (which are always sequential) to actual reset bits in the controller... Cheers! > Regards, > Lorenzo > >> >> Cheers, >> Angelo >> >>> +#define EN7581_CPU_TIMER2_RST 2 >>> +#define EN7581_HSUART_RST 3 >>> +#define EN7581_UART4_RST 4 >>> +#define EN7581_UART5_RST 5 >>> +#define EN7581_I2C2_RST 6 >>> +#define EN7581_XSI_MAC_RST 7 >>> +#define EN7581_XSI_PHY_RST 8 >>> +#define EN7581_NPU_RST 9 >>> +#define EN7581_I2S_RST 10 >>> +#define EN7581_TRNG_RST 11 >>> +#define EN7581_TRNG_MSTART_RST 12 >>> +#define EN7581_DUAL_HSI0_RST 13 >>> +#define EN7581_DUAL_HSI1_RST 14 >>> +#define EN7581_HSI_RST 15 >>> +#define EN7581_DUAL_HSI0_MAC_RST 16 >>> +#define EN7581_DUAL_HSI1_MAC_RST 17 >>> +#define EN7581_HSI_MAC_RST 18 >>> +#define EN7581_WDMA_RST 19 >>> +#define EN7581_WOE0_RST 20 >>> +#define EN7581_WOE1_RST 21 >>> +#define EN7581_HSDMA_RST 22 >>> +#define EN7581_TDMA_RST 24 >>> +#define EN7581_EMMC_RST 25 >>> +#define EN7581_SOE_RST 26 >>> +#define EN7581_PCIE2_RST 27 >>> +#define EN7581_XFP_MAC_RST 28 >>> +#define EN7581_USB_HOST_P1_RST 29 >>> +#define EN7581_USB_HOST_P1_U3_PHY_RST 30 >>> +/* RST_CTRL1 */ >>> +#define EN7581_PCM1_ZSI_ISI_RST 32 >>> +#define EN7581_FE_PDMA_RST 33 >>> +#define EN7581_FE_QDMA_RST 34 >>> +#define EN7581_PCM_SPIWP_RST 36 >>> +#define EN7581_CRYPTO_RST 38 >>> +#define EN7581_TIMER_RST 40 >>> +#define EN7581_PCM1_RST 43 >>> +#define EN7581_UART_RST 44 >>> +#define EN7581_GPIO_RST 45 >>> +#define EN7581_GDMA_RST 46 >>> +#define EN7581_I2C_MASTER_RST 48 >>> +#define EN7581_PCM2_ZSI_ISI_RST 49 >>> +#define EN7581_SFC_RST 50 >>> +#define EN7581_UART2_RST 51 >>> +#define EN7581_GDMP_RST 52 >>> +#define EN7581_FE_RST 53 >>> +#define EN7581_USB_HOST_P0_RST 54 >>> +#define EN7581_GSW_RST 55 >>> +#define EN7581_SFC2_PCM_RST 57 >>> +#define EN7581_PCIE0_RST 58 >>> +#define EN7581_PCIE1_RST 59 >>> +#define EN7581_CPU_TIMER_RST 60 >>> +#define EN7581_PCIE_HB_RST 61 >>> +#define EN7581_XPON_MAC_RST 63 >>> + >>> +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */ >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel