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Sun, 7 Sep 2025 23:50:22 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sun, 7 Sep 2025 23:50:21 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sun, 7 Sep 2025 23:50:21 -0500 Received: from [172.24.235.208] (hkshenoy.dhcp.ti.com [172.24.235.208]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5884oGt04185829; Sun, 7 Sep 2025 23:50:17 -0500 Message-ID: Date: Mon, 8 Sep 2025 10:20:15 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: ti: k3-j784s4-j742s2-main-common: Update DSS EDP integration configuration register To: Beleswar Prasad Padhi , , , , , , , , , , , , , , , , References: <20250907182806.1031544-1-h-shenoy@ti.com> <20250907182806.1031544-3-h-shenoy@ti.com> <7cf605e3-e1be-43e4-ba14-c1310b4f5869@ti.com> Content-Language: en-US From: Harikrishna Shenoy In-Reply-To: <7cf605e3-e1be-43e4-ba14-c1310b4f5869@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250907_215030_926308_A0FA26AE X-CRM114-Status: GOOD ( 13.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/8/25 10:07, Beleswar Prasad Padhi wrote: > On 07/09/25 23:58, Harikrishna Shenoy wrote: >> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in >> TRM Table 2-1 MAIN Domain Memory Map. >> Link:https://www.ti.com/lit/zip/spruj52/SPRUJ52-J84S4 AM69A TRM > > Broken link https://www.ti.com/lit/zip/spruj52 , this link will download the zip and refer the SPRUJ52-J84S4 AM69A TRM. > >> Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file") > > Above commit only refactored the changes and carried the bug. > The commit that introduced this bug should be: > > 603669b16701 arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node > > Thanks, > Beleswar Noted >> Signed-off-by: Harikrishna Shenoy >> --- >> arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi >> index fbbe768e7a30..f0cda14c2530 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi >> @@ -2573,7 +2573,7 @@ port@1 { >> mhdp: bridge@a000000 { >> compatible = "ti,j721e-mhdp8546"; >> reg = <0x0 0xa000000 0x0 0x30a00>, >> - <0x0 0x4f40000 0x0 0x20>; >> + <0x0 0x4f40000 0x0 0x100>; >> reg-names = "mhdptx", "j721e-intg"; >> clocks = <&k3_clks 217 11>; >> interrupt-parent = <&gic500>;