From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70DF1CAC5B9 for ; Mon, 29 Sep 2025 17:45:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RYV70oq/OnKMbAb5dEwpgmItKSj3Zmpmd3feYv85zac=; b=WNI+TPiykC8kkX2kEUV5iOfpx3 Xf8d5vFPUyhU8brw0bn5c6fy6cQQCHWPNnF1hx1s7VkRQs/Do3sd1ihKnwSvXmDDl3a65FTiuvuw+ cr1HY/edHQnWtG+47RKxvsbdqNhi4f9BTNOrq48p+EDZF6oRAaz/T2ludAN10Bhtn6ykK47RU6L4i arLTErWfNrHEY6tiuWDdRbImGGGHp3ttO+GbIBOnRIt5Stv0CFue/OTqA+af2fKIyt8h0obKFG9Mg JM6ys03gEtV/g9oJw77OGoccbqkWelAGwvGemcXe0PoK5yro99sNinXF6r7ahDcxfhl8DNi5VGLBj XdUoTziw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v3Hvq-00000003A1U-3agV; Mon, 29 Sep 2025 17:45:02 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v3Hvh-000000039vx-3nnh for linux-arm-kernel@lists.infradead.org; Mon, 29 Sep 2025 17:44:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 53E271BCB; Mon, 29 Sep 2025 10:44:45 -0700 (PDT) Received: from [10.1.197.69] (eglon.cambridge.arm.com [10.1.197.69]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4C6903F59E; Mon, 29 Sep 2025 10:44:48 -0700 (PDT) Message-ID: Date: Mon, 29 Sep 2025 18:44:46 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 12/29] arm_mpam: Add helpers for managing the locking around the mon_sel registers To: Jonathan Cameron Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich References: <20250910204309.20751-1-james.morse@arm.com> <20250910204309.20751-13-james.morse@arm.com> <20250911162440.0000600b@huawei.com> Content-Language: en-GB From: James Morse In-Reply-To: <20250911162440.0000600b@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250929_104454_077311_43AA3891 X-CRM114-Status: GOOD ( 17.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Jonathan, On 11/09/2025 16:24, Jonathan Cameron wrote: > On Wed, 10 Sep 2025 20:42:52 +0000 > James Morse wrote: > >> The MSC MON_SEL register needs to be accessed from hardirq for the overflow >> interrupt, and when taking an IPI to access these registers on platforms >> where MSC are not accesible from every CPU. This makes an irqsave >> spinlock the obvious lock to protect these registers. On systems with SCMI >> mailboxes it must be able to sleep, meaning a mutex must be used. The >> SCMI platforms can't support an overflow interrupt. >> >> Clearly these two can't exist for one MSC at the same time. >> >> Add helpers for the MON_SEL locking. The outer lock must be taken in a >> pre-emptible context before the inner lock can be taken. On systems with >> SCMI mailboxes where the MON_SEL accesses must sleep - the inner lock >> will fail to be 'taken' if the caller is unable to sleep. This will allow >> callers to fail without having to explicitly check the interface type of >> each MSC. > Comments talk about outer locks, but not actually seeing that in the current code. Ugh - I squashed them all together because without the DT support the DT:SCMI support ceases to be relevant, the ACPI PCC support isn't here yet, and Dave complained this was complex. I forgot to rewrite the commit message! The last paragraph is rewritten as: ------------%<------------ Add helpers for the MON_SEL locking. For now, use a irqsave spinlock and only support 'real' MMIO platforms. In the future this lock will be split in two allowing SCMI/PCC platforms to take a mutex. Because there are contexts where the SCMI/PCC platforms can't make an access, mpam_mon_sel_lock() needs to be able to fail. Do this now, so that all the error handling on these paths is present. This allows the relevant paths to fail if they are needed on a platform where this isn't possible, instead of having to make explicit checks of the interface type. ------------%<------------ It took invasive changes to make the control path safe for these firmware backed platforms. I really don't want to 'simplify' it pretending they don't exist, to then spend the following month retrofitting this. I expect the firmware backed platforms to expose one or two global MSC, so they should never hit a case where a mon_sel register access was sent via IPI. Thanks, James