Re: [PATCH 04/19] dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties

[Joseph Lo <josephl@nvidia.com>]

On 12/4/18 11:37 PM, Peter De Schrijver wrote:
> On Tue, Dec 04, 2018 at 05:25:33PM +0800, Joseph Lo wrote:
>> The cpu_lp clock property is only needed when the CPUfreq driver
>> supports CPU cluster switching. But it was not a design for this driver
>> and it didn't handle that as well. So removing this property.
>>
> 
> I would mark it optional. This means current DTs will still be
> technically compatible with this binding doc.

Hi Peter,

There is no compatible issue of this property. Because the driver 
doesn't use this clock at all. Removing this won't cause any 
backward-compatible issue.

Same as previous patch for removing vdd-cpu-supply property once we fix 
that in the driver. The old dt binding still works with the new driver.

> 
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> ---
>>   .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt   | 4 +---
>>   1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
>> index 031545a29caf..03196d5ea515 100644
>> --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
>> +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
>> @@ -9,7 +9,6 @@ Required properties:
>>     See ../clocks/clock-bindings.txt for details.
>>   - clock-names: Must include the following entries:
>>     - cpu_g: Clock mux for the fast CPU cluster.
>> -  - cpu_lp: Clock mux for the low-power CPU cluster.
>>     - pll_x: Fast PLL clocksource.
>>     - pll_p: Auxiliary PLL used during fast PLL rate changes.
>>     - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
>> @@ -30,11 +29,10 @@ cpus {
>>   		reg = <0>;
>>   
>>   		clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
>> -			 <&tegra_car TEGRA124_CLK_CCLK_LP>,
>>   			 <&tegra_car TEGRA124_CLK_PLL_X>,
>>   			 <&tegra_car TEGRA124_CLK_PLL_P>,
>>   			 <&dfll>;
>> -		clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
>> +		clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
>>   		clock-latency = <300000>;
>>   	};
>>   
>> -- 
>> 2.19.2
>>

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