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Fri, 20 Nov 2020 09:54:49 +0000 MIME-Version: 1.0 Date: Fri, 20 Nov 2020 09:54:48 +0000 From: Marc Zyngier To: Vladimir Murzin Subject: Re: AMU extension v1 support for cortex A76, A77, A78 CPUs In-Reply-To: References: <2cc9dd44-0b4b-94a8-155a-7a2446a1b892@codeaurora.org> <1712842eb0767e51155a5396d282102c@kernel.org> User-Agent: Roundcube Webmail/1.4.9 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: vladimir.murzin@arm.com, neeraju@codeaurora.org, mark.rutland@arm.com, suzuki.poulose@arm.com, ionela.voinescu@arm.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, valentin.schneider@arm.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201120_045453_025168_87E43AEB X-CRM114-Status: GOOD ( 12.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Will Deacon , suzuki.poulose@arm.com, MSM , lkml , valentin.schneider@arm.com, catalin.marinas@arm.com, ionela.voinescu@arm.com, Neeraj Upadhyay , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-11-20 09:09, Vladimir Murzin wrote: > On 11/20/20 8:56 AM, Marc Zyngier wrote: >> On 2020-11-20 04:30, Neeraj Upadhyay wrote: >>> Hi, >>> >>> For ARM cortex A76, A77, A78 cores (which as per TRM, support AMU) >>> AA64PFR0[47:44] field is not set, and AMU does not get enabled for >>> them. >>> Can you please provide support for these CPUs in cpufeature.c? >> >> If that was the case, that'd be an erratum, and it would need to be >> documented as such. It could also be that this is an optional feature >> for these cores (though the TRM doesn't suggest that). >> >> Can someone at ARM confirm what is the expected behaviour of these >> CPUs? > > Not a confirmation, but IIRC, these are imp def features, while our > cpufeatures > catches architected one. Ah, good point. So these CPUs implement some sort of AMU, and not *the* AMU. Yet the register names are the same. Who thought that'd be a good idea? M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel