From: Robin Murphy <robin.murphy@arm.com>
To: Will Deacon <will@kernel.org>
Cc: iommu@lists.linux-foundation.org, jcrouse@codeaurora.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 07/10] iommu/io-pgtable-arm: Rationalise MAIR handling
Date: Mon, 4 Nov 2019 18:43:06 +0000 [thread overview]
Message-ID: <d7d7513d-9e54-6ae8-168a-2460a306a027@arm.com> (raw)
In-Reply-To: <20191104182029.GG24909@willie-the-truck>
On 04/11/2019 18:20, Will Deacon wrote:
> On Fri, Oct 25, 2019 at 07:08:36PM +0100, Robin Murphy wrote:
>> Between VMSAv8-64 and the various 32-bit formats, there is either one
>> 64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
>> As such, keeping two 64-bit values in io_pgtable_cfg has always been
>> overkill.
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>> drivers/iommu/arm-smmu-v3.c | 2 +-
>> drivers/iommu/arm-smmu.c | 4 ++--
>> drivers/iommu/io-pgtable-arm.c | 3 +--
>> drivers/iommu/ipmmu-vmsa.c | 2 +-
>> drivers/iommu/qcom_iommu.c | 4 ++--
>> include/linux/io-pgtable.h | 2 +-
>> 6 files changed, 8 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
>> index 8da93e730d6f..3f20e548f1ec 100644
>> --- a/drivers/iommu/arm-smmu-v3.c
>> +++ b/drivers/iommu/arm-smmu-v3.c
>> @@ -2172,7 +2172,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
>> cfg->cd.asid = (u16)asid;
>> cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
>> cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
>> - cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
>> + cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair;
>> return 0;
>>
>> out_free_asid:
>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>> index 080af0326816..2bc3e93b11e6 100644
>> --- a/drivers/iommu/arm-smmu.c
>> +++ b/drivers/iommu/arm-smmu.c
>> @@ -552,8 +552,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
>> cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr;
>> cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr;
>> } else {
>> - cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
>> - cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
>> + cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair;
>> + cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair >> 32;
>
> Does this work correctly for big-endian?
I don't see why it wouldn't - cfg.mair is read and written as a u64, so
this should always return its most significant word regardless of the
storage format. We're not doing anything dodgy like trying to type-pun
the u64 directly into the u32[2].
Robin.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-04 18:43 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 18:08 [PATCH v2 00/10] iommu/io-pgtable: Cleanup and prep for split tables Robin Murphy
2019-10-25 18:08 ` [PATCH v2 01/10] iommu/io-pgtable: Make selftest gubbins consistently __init Robin Murphy
2019-10-25 18:08 ` [PATCH v2 02/10] iommu/io-pgtable-arm: Rationalise size check Robin Murphy
2019-10-25 18:08 ` [PATCH v2 03/10] iommu/io-pgtable-arm: Simplify bounds checks Robin Murphy
2019-10-25 18:08 ` [PATCH v2 04/10] iommu/io-pgtable-arm: Simplify start level lookup Robin Murphy
2019-10-25 18:08 ` [PATCH v2 05/10] iommu/io-pgtable-arm: Simplify PGD size handling Robin Murphy
2019-10-25 18:08 ` [PATCH v2 06/10] iommu/io-pgtable-arm: Simplify level indexing Robin Murphy
2019-11-04 18:17 ` Will Deacon
2019-11-04 18:36 ` Robin Murphy
2019-11-04 19:20 ` Will Deacon
2019-10-25 18:08 ` [PATCH v2 07/10] iommu/io-pgtable-arm: Rationalise MAIR handling Robin Murphy
2019-11-04 18:20 ` Will Deacon
2019-11-04 18:43 ` Robin Murphy [this message]
2019-11-04 19:20 ` Will Deacon
2019-11-04 19:57 ` Will Deacon
2019-10-25 18:08 ` [PATCH v2 08/10] iommu/io-pgtable-arm: Rationalise TTBRn handling Robin Murphy
2019-10-28 15:09 ` Steven Price
2019-10-28 18:51 ` Robin Murphy
2019-11-04 18:36 ` Will Deacon
2019-11-04 19:12 ` Robin Murphy
2019-11-22 22:40 ` Jordan Crouse
2019-10-25 18:08 ` [PATCH v2 09/10] iommu/io-pgtable-arm: Rationalise TCR handling Robin Murphy
2019-11-04 19:14 ` Will Deacon
2019-11-04 23:27 ` Jordan Crouse
2019-11-20 15:11 ` Will Deacon
2019-11-22 15:51 ` Robin Murphy
2019-11-25 7:58 ` Will Deacon
2019-11-22 22:03 ` Jordan Crouse
2019-10-25 18:08 ` [PATCH v2 10/10] iommu/io-pgtable-arm: Prepare for TTBR1 usage Robin Murphy
2019-11-04 23:40 ` Jordan Crouse
2019-11-20 19:18 ` Will Deacon
2019-11-22 22:03 ` Jordan Crouse
2019-11-04 19:22 ` [PATCH v2 00/10] iommu/io-pgtable: Cleanup and prep for split tables Will Deacon
2019-11-04 20:20 ` Will Deacon
2020-01-10 15:09 ` Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=d7d7513d-9e54-6ae8-168a-2460a306a027@arm.com \
--to=robin.murphy@arm.com \
--cc=iommu@lists.linux-foundation.org \
--cc=jcrouse@codeaurora.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox