* Re: [PATCH v4 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property [not found] ` <20220530101031.11357-2-r-ravikumar@ti.com> @ 2022-05-30 11:27 ` Krzysztof Kozlowski 2022-06-15 19:35 ` Lee Jones 1 sibling, 0 replies; 5+ messages in thread From: Krzysztof Kozlowski @ 2022-05-30 11:27 UTC (permalink / raw) To: Rahul T R, robh+dt, nm, vigneshr, kishon, krzysztof.kozlowski+dt Cc: lee.jones, rogerq, devicetree, kristo, linux-arm-kernel, linux-kernel, s-anna On 30/05/2022 12:10, Rahul T R wrote: > Add a pattern property for clock-controller, also update the example > with a clock-controller node > > Signed-off-by: Rahul T R <r-ravikumar@ti.com> > --- > .../bindings/mfd/ti,j721e-system-controller.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property [not found] ` <20220530101031.11357-2-r-ravikumar@ti.com> 2022-05-30 11:27 ` [PATCH v4 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property Krzysztof Kozlowski @ 2022-06-15 19:35 ` Lee Jones 1 sibling, 0 replies; 5+ messages in thread From: Lee Jones @ 2022-06-15 19:35 UTC (permalink / raw) To: Rahul T R Cc: nm, devicetree, vigneshr, kristo, linux-kernel, kishon, rogerq, robh+dt, krzysztof.kozlowski+dt, linux-arm-kernel On Mon, 30 May 2022, Rahul T R wrote: > Add a pattern property for clock-controller, also update the example > with a clock-controller node > > Signed-off-by: Rahul T R <r-ravikumar@ti.com> > --- > .../bindings/mfd/ti,j721e-system-controller.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Applied, thanks. -- Lee Jones [李琼斯] Principal Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <20220530101031.11357-4-r-ravikumar@ti.com>]
* Re: [PATCH v4 3/3] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header [not found] ` <20220530101031.11357-4-r-ravikumar@ti.com> @ 2022-06-18 2:16 ` Nishanth Menon 2022-06-18 12:11 ` Jason Kridner 0 siblings, 1 reply; 5+ messages in thread From: Nishanth Menon @ 2022-06-18 2:16 UTC (permalink / raw) To: Rahul T R Cc: devicetree, vigneshr, kristo, robertcnelson, linux-kernel, jkridner, kishon, rogerq, robh+dt, krzysztof.kozlowski+dt, vijayp, lee.jones, linux-arm-kernel On 15:40-20220530, Rahul T R wrote: > From: Sinthu Raja <sinthu.raja@ti.com> > > Add pinmux required to bring out > i2c5, ehrpwm 2 and 3 and gpios on > 40 pin RPi header on sk board > > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> > Signed-off-by: Rahul T R <r-ravikumar@ti.com> I was digging deeper at https://www.ti.com/lit/zip/sprr438 (PROC112E2(001)_SCH.pdf - J3, Also looking at https://github.com/beagleboard/beaglebone-ai-64/blob/master/BeagleBone%20AI%20-64_SCH_V1.02_211119.pdf (P8, P9) And comparing it to https://www.raspberrypi-spy.co.uk/2012/06/simple-guide-to-the-rpi-gpio-header-and-pins/ And considering potential use such as https://pypi.org/project/RPi.GPIO/ variation, Here is my suggestion (applies to other TI Boards that attempt to emulate RPI header) a) Default mux in board.dts should be GPIO except for the i2c used for ID detection. b) Secondary functions should be a dt overlay. (These can easily enable the pwms and other functions as needed) c) Maintain node names consistent to allow reuse of overlays across platforms. Usage: you can either use extlinux.conf OR uEnv.txt to apply the overlays as desired (ID detection from hats might help automate it based on the bootloader you'd want to use) Else, you have created a custom configuration here for 1 specific application, various hats that expect GPIO will end up croaking. I am open to discussions here. > --- > arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 89 ++++++++++++++++++++++---- > 1 file changed, 78 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > index 98a55778f3fe..b913b18ae133 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > @@ -400,6 +400,57 @@ > J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ > >; > }; > + > + main_i2c5_pins_default: main-i2c5-pins-default { > + pinctrl-single,pins = < > + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ > + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ > + >; > + }; > + > + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { > + pinctrl-single,pins = < > + J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ > + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ > + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ > + J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ > + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ > + J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ > + J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ > + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ > + J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ > + J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ > + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ > + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ > + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ > + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ > + J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ > + J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ > + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ > + J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ > + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ > + >; > + }; > + > + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { > + pinctrl-single,pins = < > + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ > + >; > + }; > + > + rpi_header_ehrpwm2_pins_default: rpi-header-ehrpwm2-pins-default { > + pinctrl-single,pins = < > + J721E_IOPAD(0x178, PIN_INPUT, 6) /* (U27) RGMII5_RD3.EHRPWM2_A */ > + J721E_IOPAD(0x17c, PIN_INPUT, 6) /* (U24) RGMII5_RD2.EHRPWM2_B */ > + >; > + }; > + > + rpi_header_ehrpwm3_pins_default: rpi-header-ehrpwm3-pins-default { > + pinctrl-single,pins = < > + J721E_IOPAD(0x18c, PIN_INPUT, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */ > + J721E_IOPAD(0x190, PIN_INPUT, 6) /* (W23) RGMII6_TD3.EHRPWM3_B */ > + >; > + }; > }; > > &wkup_pmx0 { > @@ -631,11 +682,6 @@ > status = "disabled"; > }; > > -&main_i2c5 { > - /* Brought out on RPi Header */ > - status = "disabled"; > -}; > - Please don't relocate nodes in the same patch - kinda messes up the diffstat and makes review a bit harder. > &main_i2c6 { > /* Unused */ > status = "disabled"; > @@ -1138,18 +1184,39 @@ > status = "disabled"; > }; > > -&main_ehrpwm2 { > +&main_ehrpwm4 { > status = "disabled"; > }; > > -&main_ehrpwm3 { > +&main_ehrpwm5 { > status = "disabled"; > }; > > -&main_ehrpwm4 { > - status = "disabled"; > +&main_gpio0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&rpi_header_gpio0_pins_default>; > }; > > -&main_ehrpwm5 { > - status = "disabled"; > +&main_gpio1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&rpi_header_gpio1_pins_default>; > +}; > + > +&main_i2c5 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_i2c5_pins_default>; > + clock-frequency = <400000>; > + status = "okay"; Defaults in SoC.dtsi so far are "okay" - so adding that again is superfluous This happens when you are relocating nodes etc > +}; > + > +&main_ehrpwm2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&rpi_header_ehrpwm2_pins_default>; > + status = "okay"; > +}; > + > +&main_ehrpwm3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&rpi_header_ehrpwm3_pins_default>; > + status = "okay"; > }; -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4 3/3] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header 2022-06-18 2:16 ` [PATCH v4 3/3] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header Nishanth Menon @ 2022-06-18 12:11 ` Jason Kridner 0 siblings, 0 replies; 5+ messages in thread From: Jason Kridner @ 2022-06-18 12:11 UTC (permalink / raw) To: Nishanth Menon Cc: devicetree, Rahul T R, kristo, Robert Nelson, linux-kernel, Kishon Vijay Abraham, rogerq, Rob Herring, krzysztof.kozlowski+dt, Pothukuchi, Vijay, lee.jones, ARM Kernel List, Raghavendra, Vignesh For those seeing this message multiple times, my apologies for not properly setting up my mailer. On Fri, Jun 17, 2022 at 10:16 PM Nishanth Menon <nm@ti.com> wrote: > > On 15:40-20220530, Rahul T R wrote: > > From: Sinthu Raja <sinthu.raja@ti.com> > > > > Add pinmux required to bring out > > i2c5, ehrpwm 2 and 3 and gpios on > > 40 pin RPi header on sk board > > > > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> > > Signed-off-by: Rahul T R <r-ravikumar@ti.com> > > > I was digging deeper at https://www.ti.com/lit/zip/sprr438 > (PROC112E2(001)_SCH.pdf - J3, Also looking at > https://github.com/beagleboard/beaglebone-ai-64/blob/master/BeagleBone%20AI%20-64_SCH_V1.02_211119.pdf > (P8, P9) > > And comparing it to https://www.raspberrypi-spy.co.uk/2012/06/simple-guide-to-the-rpi-gpio-header-and-pins/ > And considering potential use such as https://pypi.org/project/RPi.GPIO/ > variation, > > Here is my suggestion (applies to other TI Boards that attempt to > emulate RPI header) > a) Default mux in board.dts should be GPIO except for the i2c used for > ID detection. > b) Secondary functions should be a dt overlay. (These can easily enable > the pwms and other functions as needed) > c) Maintain node names consistent to allow reuse of overlays across > platforms. > > Usage: you can either use extlinux.conf OR uEnv.txt to apply the > overlays as desired (ID detection from hats might help automate it based > on the bootloader you'd want to use) > > Else, you have created a custom configuration here for 1 specific > application, various hats that expect GPIO will end up croaking. > > > I am open to discussions here. A read of our recent blog series done with Bootlin is worth a read on this topic. https://bbb.io/@2804 My suggestion is to put the entries for the common functions in the base tree, but not enable them (except for the I2C used for ID detection, as you suggested). This can remove SoC-specific requirements on the overlays such that the overlays are written against a header specification as defined by the common symbols provided. So, make the entries in the base tree and leave them "disabled" such that overlays only need to set the symbol to "okay", at least for the common stuff to all implementations of the Pi header. > > > > --- > > arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 89 ++++++++++++++++++++++---- > > 1 file changed, 78 insertions(+), 11 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > > index 98a55778f3fe..b913b18ae133 100644 > > --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > > +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > > @@ -400,6 +400,57 @@ > > J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ > > >; > > }; > > + > > + main_i2c5_pins_default: main-i2c5-pins-default { > > + pinctrl-single,pins = < > > + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ > > + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ > > + >; > > + }; > > + > > + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { > > + pinctrl-single,pins = < > > + J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ > > + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ > > + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ > > + J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ > > + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ > > + J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ > > + J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ > > + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ > > + J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ > > + J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ > > + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ > > + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ > > + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ > > + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ > > + J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ > > + J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ > > + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ > > + J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ > > + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ > > + >; > > + }; > > + > > + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { > > + pinctrl-single,pins = < > > + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ > > + >; > > + }; > > + > > + rpi_header_ehrpwm2_pins_default: rpi-header-ehrpwm2-pins-default { > > + pinctrl-single,pins = < > > + J721E_IOPAD(0x178, PIN_INPUT, 6) /* (U27) RGMII5_RD3.EHRPWM2_A */ > > + J721E_IOPAD(0x17c, PIN_INPUT, 6) /* (U24) RGMII5_RD2.EHRPWM2_B */ > > + >; > > + }; > > + > > + rpi_header_ehrpwm3_pins_default: rpi-header-ehrpwm3-pins-default { > > + pinctrl-single,pins = < > > + J721E_IOPAD(0x18c, PIN_INPUT, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */ > > + J721E_IOPAD(0x190, PIN_INPUT, 6) /* (W23) RGMII6_TD3.EHRPWM3_B */ > > + >; > > + }; > > }; > > > > &wkup_pmx0 { > > @@ -631,11 +682,6 @@ > > status = "disabled"; > > }; > > > > -&main_i2c5 { > > - /* Brought out on RPi Header */ > > - status = "disabled"; > > -}; > > - > > Please don't relocate nodes in the same patch - kinda messes up the > diffstat and makes review a bit harder. > > > &main_i2c6 { > > /* Unused */ > > status = "disabled"; > > @@ -1138,18 +1184,39 @@ > > status = "disabled"; > > }; > > > > -&main_ehrpwm2 { > > +&main_ehrpwm4 { > > status = "disabled"; > > }; > > > > -&main_ehrpwm3 { > > +&main_ehrpwm5 { > > status = "disabled"; > > }; > > > > -&main_ehrpwm4 { > > - status = "disabled"; > > +&main_gpio0 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&rpi_header_gpio0_pins_default>; > > }; > > > > -&main_ehrpwm5 { > > - status = "disabled"; > > +&main_gpio1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&rpi_header_gpio1_pins_default>; > > +}; > > + > > +&main_i2c5 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&main_i2c5_pins_default>; > > + clock-frequency = <400000>; > > + status = "okay"; > > Defaults in SoC.dtsi so far are "okay" - so adding that again is > superfluous This happens when you are relocating nodes etc > > > +}; > > + > > +&main_ehrpwm2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&rpi_header_ehrpwm2_pins_default>; > > + status = "okay"; > > +}; > > + > > +&main_ehrpwm3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&rpi_header_ehrpwm3_pins_default>; > > + status = "okay"; > > }; > > -- > Regards, > Nishanth Menon > Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D -- https://beagleboard.org/about/jkridner - a 501c3 non-profit educating around open hardware computing _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <20220530101031.11357-3-r-ravikumar@ti.com>]
* Re: [PATCH v4 2/3] arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs [not found] ` <20220530101031.11357-3-r-ravikumar@ti.com> @ 2022-06-18 2:19 ` Nishanth Menon 0 siblings, 0 replies; 5+ messages in thread From: Nishanth Menon @ 2022-06-18 2:19 UTC (permalink / raw) To: Rahul T R Cc: devicetree, vigneshr, kristo, linux-kernel, kishon, rogerq, robh+dt, krzysztof.kozlowski+dt, Vijay Pothukuchi, lee.jones, linux-arm-kernel On 15:40-20220530, Rahul T R wrote: > From: Vijay Pothukuchi <vijayp@ti.com> > > Add dts nodes for 6 EHRPWM instances on SoC > > Signed-off-by: Vijay Pothukuchi <vijayp@ti.com> > Signed-off-by: Rahul T R <r-ravikumar@ti.com> > --- > .../dts/ti/k3-j721e-common-proc-board.dts | 24 +++++++ > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 62 ++++++++++++++++++- > arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 +++++++ > 3 files changed, 109 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts > index 2bc26a296496..f7d02fa4d6fc 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts > @@ -995,3 +995,27 @@ > &main_mcan13 { > status = "disabled"; > }; > + > +&main_ehrpwm0 { > + status = "disabled"; > +}; > + > +&main_ehrpwm1 { > + status = "disabled"; > +}; > + > +&main_ehrpwm2 { > + status = "disabled"; > +}; > + > +&main_ehrpwm3 { > + status = "disabled"; > +}; > + > +&main_ehrpwm4 { > + status = "disabled"; > +}; > + > +&main_ehrpwm5 { > + status = "disabled"; > +}; Do the pwm driver croak and die OR it is un-usable on proc-board or disabled due to not-primary function (ideally drivers should shut things off when unused)? > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > index 43b6cf5791ee..1ee00b73905d 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > @@ -66,7 +66,67 @@ > #mux-control-cells = <1>; > mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ > <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ > - }; > + }; > + > + ehrpwm_tbclk: clock-controller@4140 { > + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; > + reg = <0x4140 0x18>; > + #clock-cells = <1>; > + }; > + }; > + > + main_ehrpwm0: pwm@3000000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x0 0x3000000 0x0 0x100>; would suggest 0x00 instead of 0x0 > + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; > + clock-names = "tbclk", "fck"; > + }; > + > + main_ehrpwm1: pwm@3010000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x0 0x3010000 0x0 0x100>; > + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; > + clock-names = "tbclk", "fck"; > + }; > + > + main_ehrpwm2: pwm@3020000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x0 0x3020000 0x0 0x100>; > + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; > + clock-names = "tbclk", "fck"; > + }; > + > + main_ehrpwm3: pwm@3030000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x0 0x3030000 0x0 0x100>; > + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; > + clock-names = "tbclk", "fck"; > + }; > + > + main_ehrpwm4: pwm@3040000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x0 0x3040000 0x0 0x100>; > + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; > + clock-names = "tbclk", "fck"; > + }; > + > + main_ehrpwm5: pwm@3050000 { > + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; > + #pwm-cells = <3>; > + reg = <0x0 0x3050000 0x0 0x100>; > + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; > + clock-names = "tbclk", "fck"; > }; > > gic500: interrupt-controller@1800000 { > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > index 80358cba6954..98a55778f3fe 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts > @@ -1129,3 +1129,27 @@ > memory-region = <&c71_0_dma_memory_region>, > <&c71_0_memory_region>; > }; > + > +&main_ehrpwm0 { > + status = "disabled"; > +}; > + > +&main_ehrpwm1 { > + status = "disabled"; > +}; > + > +&main_ehrpwm2 { > + status = "disabled"; > +}; > + > +&main_ehrpwm3 { > + status = "disabled"; > +}; > + > +&main_ehrpwm4 { > + status = "disabled"; > +}; > + > +&main_ehrpwm5 { > + status = "disabled"; > +}; > -- > 2.17.1 > -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
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[not found] <20220530101031.11357-1-r-ravikumar@ti.com>
[not found] ` <20220530101031.11357-2-r-ravikumar@ti.com>
2022-05-30 11:27 ` [PATCH v4 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property Krzysztof Kozlowski
2022-06-15 19:35 ` Lee Jones
[not found] ` <20220530101031.11357-4-r-ravikumar@ti.com>
2022-06-18 2:16 ` [PATCH v4 3/3] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header Nishanth Menon
2022-06-18 12:11 ` Jason Kridner
[not found] ` <20220530101031.11357-3-r-ravikumar@ti.com>
2022-06-18 2:19 ` [PATCH v4 2/3] arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs Nishanth Menon
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