From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD036C4338F for ; Wed, 28 Jul 2021 05:31:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8E64960724 for ; Wed, 28 Jul 2021 05:31:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:References: Cc:To:From:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QvGB6jBjDZ4eSfjUN5OqnDwzWsIsluwEfub6XoALd+k=; b=qmQVxn0Swjc16ACjpRcjokdZdE /B7qlNKhYMatnw30vth7LNyo8lRo7IiT7zH3Qg/2L0fU3OCwLRs/N/MaYcrIC0KWifBnCyVPYQzyv rbiCT9zDZg00UqOcGrYQ4m8FJ4a+Zjv9KlbV4yF4P+vn2KsPBSSANVg3sU2SrGhR3+4Z+989ksa9B JmonbzVC0QLWnxi/HNNyA0wjQoLk5uZbCfF2ZGzXIrLWA3o/u3gkaSefwpg00PyXjRxR3tQHVh9Cq KVig18PjQwTc1H7S6p5IyLjTwI7bqaDSSD4lLe9XG2EKkXPQH1s6K7BPwNhSshQia9amukh4jWF0N hiJKY16Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m8c8A-00H8fU-Fw; Wed, 28 Jul 2021 05:29:22 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m8c86-00H8ei-KE for linux-arm-kernel@lists.infradead.org; Wed, 28 Jul 2021 05:29:20 +0000 Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 28 Jul 2021 14:29:17 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 50848205902A; Wed, 28 Jul 2021 14:29:17 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 28 Jul 2021 14:29:17 +0900 Received: from yuzu2.css.socionext.com (yuzu2 [172.31.9.57]) by iyokan2.css.socionext.com (Postfix) with ESMTP id C9FB3B6392; Wed, 28 Jul 2021 14:29:16 +0900 (JST) Received: from [10.212.30.196] (unknown [10.212.30.196]) by yuzu2.css.socionext.com (Postfix) with ESMTP id 07942B1D52; Wed, 28 Jul 2021 14:29:15 +0900 (JST) Subject: Re: [PATCH v8 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER From: Kunihiko Hayashi To: Lorenzo Pieralisi , =?UTF-8?Q?Pali_Roh=c3=a1r?= Cc: Bjorn Helgaas , Bjorn Helgaas , Rob Herring , Jingoo Han , Gustavo Pimentel , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Masami Hiramatsu , linux-arm-kernel@lists.infradead.org References: <1603848703-21099-4-git-send-email-hayashi.kunihiko@socionext.com> <20201124232037.GA595463@bjorn-Precision-5520> <20201125102328.GA31700@e121166-lin.cambridge.arm.com> <20210718005109.6xwe3z7gxhuop5xc@pali> <2dfa5ec9-2a33-ae72-3904-999d8b8a2f71@socionext.com> <20210722172627.i4n65lrz3j7pduiz@pali> <17c6eeee-692f-2e9a-5827-34f6939a21a6@socionext.com> <20210723083702.nvhurkgbzbvrrmv3@pali> <660e8597-bb7a-b5a0-e3d4-f108a211ae76@socionext.com> Message-ID: Date: Wed, 28 Jul 2021 14:29:15 +0900 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <660e8597-bb7a-b5a0-e3d4-f108a211ae76@socionext.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210727_222918_842121_049432E6 X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Lorenzo, Pali, On 2021/07/23 18:36, Kunihiko Hayashi wrote: > Hi Pali, [snip] >> Just you need to specify that new/private IRQ domain into >> irq_find_mapping() call. > > I'll try to replace the events with new IRQ domain. According to Pali's suggestion, the bridge handles INTX and it isn't difficult to change IRQ's map for Root Port like the example. It seems that it can't be applied to MSI. On the other hand, according to Lorenzo's suggestion, >>>>>>> IMO this should be modelled with a separate IRQ domain and chip for >>>>>>> the root port (yes this implies describing the root port in the dts >>>>>>> file with a separate msi-parent). Interrupts for PME/AER event is assigned to number 0 of MSI IRQ domain. (pcie_port_enable_irq_vec() in portdrv_core.c) This expects MSI status bit 0 to be set when the event occurs. However, in the uniphier PCIe controller, MSI status bit 0 is not set, but the PME/AER status bit in the glue logic is set. I think that it's hard to associate the new domain and "MSI-IRQ 0" event if the new IRQ domain and chip is modelled. So, I have no idea to handle both new IRQ domain and cascaded MSI event. Is there any example for that? Thank you, --- Best Regards Kunihiko Hayashi _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel