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Thu, 03 Sep 2020 00:55:37 -0400 X-MC-Unique: XrNZi_vzOH-WTNCbZtQqog-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1A91D801FC6; Thu, 3 Sep 2020 04:55:36 +0000 (UTC) Received: from [10.64.54.159] (vpn2-54-159.bne.redhat.com [10.64.54.159]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E447B8118C; Thu, 3 Sep 2020 04:55:33 +0000 (UTC) Subject: Re: [PATCH v3 16/21] KVM: arm64: Add support for relaxing stage-2 perms in generic page-table code To: Will Deacon , kvmarm@lists.cs.columbia.edu References: <20200825093953.26493-1-will@kernel.org> <20200825093953.26493-17-will@kernel.org> From: Gavin Shan Message-ID: Date: Thu, 3 Sep 2020 14:55:31 +1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20200825093953.26493-17-will@kernel.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=gshan@redhat.com X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200903_005541_523799_5E25DA7A X-CRM114-Status: GOOD ( 21.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Gavin Shan Cc: Suzuki Poulose , Marc Zyngier , Quentin Perret , James Morse , Catalin Marinas , kernel-team@android.com, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 8/25/20 7:39 PM, Will Deacon wrote: > Add support for relaxing the permissions of a stage-2 mapping (i.e. > adding additional permissions) to the generic page-table code. > > Cc: Marc Zyngier > Cc: Quentin Perret > Signed-off-by: Will Deacon > --- > arch/arm64/include/asm/kvm_pgtable.h | 17 +++++++++++++++++ > arch/arm64/kvm/hyp/pgtable.c | 20 ++++++++++++++++++++ > 2 files changed, 37 insertions(+) > Reviewed-by: Gavin Shan > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > index ea823fe31913..0d7077c34152 100644 > --- a/arch/arm64/include/asm/kvm_pgtable.h > +++ b/arch/arm64/include/asm/kvm_pgtable.h > @@ -216,6 +216,23 @@ kvm_pte_t kvm_pgtable_stage2_mkyoung(struct kvm_pgtable *pgt, u64 addr); > */ > kvm_pte_t kvm_pgtable_stage2_mkold(struct kvm_pgtable *pgt, u64 addr); > > +/** > + * kvm_pgtable_stage2_relax_perms() - Relax the permissions enforced by a > + * page-table entry. > + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init(). > + * @addr: Intermediate physical address to identify the page-table entry. > + * @prot: Additional permissions to grant for the mapping. > + * > + * If there is a valid, leaf page-table entry used to translate @addr, then > + * relax the permissions in that entry according to the read, write and > + * execute permissions specified by @prot. No permissions are removed, and > + * TLB invalidation is performed after updating the entry. > + * > + * Return: 0 on success, negative error code on failure. > + */ > +int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr, > + enum kvm_pgtable_prot prot); > + > /** > * kvm_pgtable_stage2_is_young() - Test whether a page-table entry has the > * access flag set. > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index 75887185f1e2..6e8ca1ec12b4 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -762,6 +762,26 @@ bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr) > return pte & KVM_PTE_LEAF_ATTR_LO_S2_AF; > } > > +int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr, > + enum kvm_pgtable_prot prot) > +{ > + int ret; > + kvm_pte_t set = 0, clr = 0; > + > + if (prot & KVM_PGTABLE_PROT_R) > + set |= KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R; > + > + if (prot & KVM_PGTABLE_PROT_W) > + set |= KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W; > + > + if (prot & KVM_PGTABLE_PROT_X) > + clr |= KVM_PTE_LEAF_ATTR_HI_S2_XN; > + > + ret = stage2_update_leaf_attrs(pgt, addr, 1, set, clr, NULL); > + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, pgt->mmu, addr, 0); > + return ret; > +} > + > static int stage2_flush_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, > enum kvm_pgtable_walk_flags flag, > void * const arg) > Thanks, Gavin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel