From: Eric Auger <eauger@redhat.com>
To: Reiji Watanabe <reijiw@google.com>, Marc Zyngier <maz@kernel.org>,
kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, Will Deacon <will@kernel.org>,
Peter Shier <pshier@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH v3 02/29] KVM: arm64: Save ID registers' sanitized value per vCPU
Date: Thu, 18 Nov 2021 21:36:58 +0100 [thread overview]
Message-ID: <dad16d0f-a0fa-cd8e-fdd0-0bbdf38af791@redhat.com> (raw)
In-Reply-To: <20211117064359.2362060-3-reijiw@google.com>
Hi Reiji,
On 11/17/21 7:43 AM, Reiji Watanabe wrote:
> Extend sys_regs[] of kvm_cpu_context for ID registers and save ID
> registers' sanitized value in the array for the vCPU at the first
> vCPU reset. Use the saved ones when ID registers are read by
> userspace (via KVM_GET_ONE_REG) or the guest.
>
> Signed-off-by: Reiji Watanabe <reijiw@google.com>
> ---
> arch/arm64/include/asm/kvm_host.h | 10 +++++++
> arch/arm64/kvm/sys_regs.c | 43 +++++++++++++++++++------------
> 2 files changed, 37 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index edbe2cb21947..72db73c79403 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -146,6 +146,14 @@ struct kvm_vcpu_fault_info {
> u64 disr_el1; /* Deferred [SError] Status Register */
> };
>
> +/*
> + * (Op0, Op1, CRn, CRm, Op2) of ID registers is (3, 0, 0, crm, op2),
> + * where 0<=crm<8, 0<=op2<8.
> + */
> +#define KVM_ARM_ID_REG_MAX_NUM 64
> +#define IDREG_IDX(id) ((sys_reg_CRm(id) << 3) | sys_reg_Op2(id))
> +#define IDREG_SYS_IDX(id) (ID_REG_BASE + IDREG_IDX(id))
> +
> enum vcpu_sysreg {
> __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
> MPIDR_EL1, /* MultiProcessor Affinity Register */
> @@ -210,6 +218,8 @@ enum vcpu_sysreg {
> CNTP_CVAL_EL0,
> CNTP_CTL_EL0,
>
> + ID_REG_BASE,
> + ID_REG_END = ID_REG_BASE + KVM_ARM_ID_REG_MAX_NUM - 1,
> /* Memory Tagging Extension registers */
> RGSR_EL1, /* Random Allocation Tag Seed Register */
> GCR_EL1, /* Tag Control Register */
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index e3ec1a44f94d..5608d3410660 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -33,6 +33,8 @@
>
> #include "trace.h"
>
> +static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id);
> +
> /*
> * All of this file is extremely similar to the ARM coproc.c, but the
> * types are different. My gut feeling is that it should be pretty
> @@ -273,7 +275,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu,
> struct sys_reg_params *p,
> const struct sys_reg_desc *r)
> {
> - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
> + u64 val = __read_id_reg(vcpu, SYS_ID_AA64MMFR1_EL1);
> u32 sr = reg_to_encoding(r);
>
> if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
> @@ -1059,17 +1061,9 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
> return true;
> }
>
> -/* Read a sanitised cpufeature ID register by sys_reg_desc */
> -static u64 read_id_reg(const struct kvm_vcpu *vcpu,
> - struct sys_reg_desc const *r, bool raz)
> +static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> {
> - u32 id = reg_to_encoding(r);
> - u64 val;
> -
> - if (raz)
> - return 0;
> -
> - val = read_sanitised_ftr_reg(id);
> + u64 val = __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id));
>
> switch (id) {
> case SYS_ID_AA64PFR0_EL1:
> @@ -1119,6 +1113,14 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
> return val;
> }
>
> +static u64 read_id_reg(const struct kvm_vcpu *vcpu,
> + struct sys_reg_desc const *r, bool raz)
> +{
> + u32 id = reg_to_encoding(r);
> +
> + return raz ? 0 : __read_id_reg(vcpu, id);
> +}
> +
> static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *r)
> {
> @@ -1178,6 +1180,16 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
> return REG_HIDDEN;
> }
>
> +static void reset_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
> +{
> + u32 id = reg_to_encoding(rd);
> +
> + if (vcpu_has_reset_once(vcpu))
> + return;
> +
> + __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id)) = read_sanitised_ftr_reg(id);
> +}
> +
> static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd,
> const struct kvm_one_reg *reg, void __user *uaddr)
> @@ -1223,9 +1235,7 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> /*
> * cpufeature ID register user accessors
> *
> - * For now, these registers are immutable for userspace, so no values
> - * are stored, and for set_id_reg() we don't allow the effective value
> - * to be changed.
> + * We don't allow the effective value to be changed.
This change may be moved to a subsequent patch as this patch does not
change the behavior yet.
> */
> static int __get_id_reg(const struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd, void __user *uaddr,
> @@ -1382,6 +1392,7 @@ static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
> #define ID_SANITISED(name) { \
> SYS_DESC(SYS_##name), \
> .access = access_id_reg, \
> + .reset = reset_id_reg, \
> .get_user = get_id_reg, \
> .set_user = set_id_reg, \
> .visibility = id_visibility, \
> @@ -1837,8 +1848,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
> if (p->is_write) {
> return ignore_write(vcpu, p);
> } else {
> - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
> - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
> + u64 dfr = __read_id_reg(vcpu, SYS_ID_AA64DFR0_EL1);
> + u64 pfr = __read_id_reg(vcpu, SYS_ID_AA64PFR0_EL1);
> u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
>
> p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
>
Thanks
Eric
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next prev parent reply other threads:[~2021-11-18 20:38 UTC|newest]
Thread overview: 109+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-17 6:43 [RFC PATCH v3 00/29] KVM: arm64: Make CPU ID registers writable by userspace Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 01/29] KVM: arm64: Add has_reset_once flag for vcpu Reiji Watanabe
2021-11-21 12:36 ` Marc Zyngier
2021-11-23 0:51 ` Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 02/29] KVM: arm64: Save ID registers' sanitized value per vCPU Reiji Watanabe
2021-11-18 20:36 ` Eric Auger [this message]
2021-11-18 22:00 ` Reiji Watanabe
2021-11-24 18:08 ` Eric Auger
2021-11-21 12:36 ` Marc Zyngier
2021-11-23 4:39 ` Reiji Watanabe
2021-11-23 10:03 ` Marc Zyngier
2021-11-23 17:12 ` Reiji Watanabe
2021-12-02 10:58 ` Eric Auger
2021-12-04 1:45 ` Reiji Watanabe
2021-12-07 9:34 ` Eric Auger
2021-12-08 5:57 ` Reiji Watanabe
2021-12-08 7:09 ` Eric Auger
2021-12-08 7:18 ` Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 03/29] KVM: arm64: Introduce struct id_reg_info Reiji Watanabe
2021-11-18 20:36 ` Eric Auger
2021-11-19 4:47 ` Reiji Watanabe
2021-11-21 12:37 ` Marc Zyngier
2021-11-23 0:56 ` Reiji Watanabe
2021-11-24 18:22 ` Eric Auger
2021-11-25 6:05 ` Reiji Watanabe
2021-11-21 12:37 ` Marc Zyngier
2021-11-25 5:27 ` Reiji Watanabe
2021-12-01 15:38 ` Alexandru Elisei
2021-12-02 4:32 ` Reiji Watanabe
2021-11-24 21:07 ` Eric Auger
2021-11-25 6:40 ` Reiji Watanabe
2021-12-02 12:51 ` Eric Auger
2021-12-01 15:24 ` Alexandru Elisei
2021-12-02 4:09 ` Reiji Watanabe
2021-12-02 12:51 ` Eric Auger
2021-12-04 4:35 ` Reiji Watanabe
2021-12-07 9:36 ` Eric Auger
2021-11-17 6:43 ` [RFC PATCH v3 04/29] KVM: arm64: Make ID_AA64PFR0_EL1 writable Reiji Watanabe
2021-11-21 12:37 ` Marc Zyngier
2021-11-24 6:11 ` Reiji Watanabe
2021-11-25 15:35 ` Eric Auger
2021-11-30 1:29 ` Reiji Watanabe
2021-12-02 13:02 ` Eric Auger
2021-12-04 7:59 ` Reiji Watanabe
2021-12-07 9:42 ` Eric Auger
2021-11-17 6:43 ` [RFC PATCH v3 05/29] KVM: arm64: Make ID_AA64PFR1_EL1 writable Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 06/29] KVM: arm64: Make ID_AA64ISAR0_EL1 writable Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 07/29] KVM: arm64: Make ID_AA64ISAR1_EL1 writable Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 08/29] KVM: arm64: Make ID_AA64MMFR0_EL1 writable Reiji Watanabe
2021-11-25 15:31 ` Eric Auger
2021-11-30 4:43 ` Reiji Watanabe
2021-11-25 16:06 ` Eric Auger
2021-11-17 6:43 ` [RFC PATCH v3 09/29] KVM: arm64: Hide IMPLEMENTATION DEFINED PMU support for the guest Reiji Watanabe
2021-11-25 20:30 ` Eric Auger
2021-11-30 5:32 ` Reiji Watanabe
2021-12-01 15:53 ` Alexandru Elisei
2021-12-01 16:09 ` Alexandru Elisei
2021-12-02 4:42 ` Reiji Watanabe
2021-12-02 10:57 ` Eric Auger
2021-12-04 1:04 ` Reiji Watanabe
2021-12-04 14:14 ` Eric Auger
2021-12-04 17:39 ` Reiji Watanabe
2021-12-04 23:38 ` Itaru Kitayama
2021-12-06 0:27 ` Reiji Watanabe
2021-12-06 9:52 ` Alexandru Elisei
2021-12-06 10:25 ` Eric Auger
2021-12-07 7:07 ` Reiji Watanabe
2021-12-07 8:10 ` Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 10/29] KVM: arm64: Make ID_AA64DFR0_EL1 writable Reiji Watanabe
2021-11-25 20:30 ` Eric Auger
2021-11-30 5:21 ` Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 11/29] KVM: arm64: Make ID_DFR0_EL1 writable Reiji Watanabe
2021-11-24 13:46 ` Eric Auger
2021-11-25 5:33 ` Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 12/29] KVM: arm64: Make ID_DFR1_EL1 writable Reiji Watanabe
2021-11-25 20:30 ` Eric Auger
2021-11-30 5:39 ` Reiji Watanabe
2021-12-02 13:11 ` Eric Auger
2021-11-17 6:43 ` [RFC PATCH v3 13/29] KVM: arm64: Make ID_MMFR0_EL1 writable Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 14/29] KVM: arm64: Make MVFR1_EL1 writable Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 15/29] KVM: arm64: Make ID registers without id_reg_info writable Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 16/29] KVM: arm64: Add consistency checking for frac fields of ID registers Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 17/29] KVM: arm64: Introduce KVM_CAP_ARM_ID_REG_CONFIGURABLE capability Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 18/29] KVM: arm64: Add kunit test for ID register validation Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 19/29] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 20/29] KVM: arm64: Use vcpu->arch.mdcr_el2 to track value of mdcr_el2 Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 21/29] KVM: arm64: Introduce framework to trap disabled features Reiji Watanabe
2021-11-21 18:46 ` Marc Zyngier
2021-11-23 7:27 ` Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 22/29] KVM: arm64: Trap disabled features of ID_AA64PFR0_EL1 Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 23/29] KVM: arm64: Trap disabled features of ID_AA64PFR1_EL1 Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 24/29] KVM: arm64: Trap disabled features of ID_AA64DFR0_EL1 Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 25/29] KVM: arm64: Trap disabled features of ID_AA64MMFR1_EL1 Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 26/29] KVM: arm64: Trap disabled features of ID_AA64ISAR1_EL1 Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 27/29] KVM: arm64: Initialize trapping of disabled CPU features for the guest Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 28/29] KVM: arm64: Add kunit test for trap initialization Reiji Watanabe
2021-11-17 6:43 ` [RFC PATCH v3 29/29] KVM: arm64: selftests: Introduce id_reg_test Reiji Watanabe
2021-11-18 20:34 ` Eric Auger
2021-11-20 6:39 ` Reiji Watanabe
2021-11-22 14:17 ` Eric Auger
2021-11-23 6:33 ` Reiji Watanabe
2021-11-23 16:00 ` [RFC PATCH v3 00/29] KVM: arm64: Make CPU ID registers writable by userspace Alexandru Elisei
2021-11-24 5:13 ` Reiji Watanabe
2021-11-24 10:50 ` Alexandru Elisei
2021-11-24 17:00 ` Reiji Watanabe
2021-11-23 16:27 ` Alexandru Elisei
2021-11-24 5:49 ` Reiji Watanabe
2021-11-24 10:48 ` Alexandru Elisei
2021-11-24 16:44 ` Reiji Watanabe
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