Re: [PATCH] PCI: Mark Nvidia GB10 to avoid bus reset

[Terje Bergstrom <tbergstrom@nvidia.com>]

On 1/14/26 09:28, Bjorn Helgaas wrote:

> What sort of crash happens?  It's useful if we can include a bread > crumb that will help people identify the crash and find a fix.
We observed retraining to lower PCIe lane count and config read timeout.
So yes crash is not the best way to describe it.

> I'm confused about what the topology is.  I first assumed GB10 was > a PCIe Endpoint, since Secondary Bus Reset only applies to devices > below a bridge, so SBR would be applied to a device by a config > write to that bridge.
gb10 is an SoC designed by NVIDIA and Mediatek in collaboration. It's
not an endpoint, but has its own PCIe controller for connecting PCIe
peripherals like NVMe drives, NIC, etc.

> If this is actually a GB10 issue, it sounds like a hardware erratum > that lots of users would see and Nvidia would likely be aware of.
We're aware. We've maintained a quirk in a kernel tree for DGX Spark 
and other gb10 powered products until this gets upstreamed.

Terje