Re: [PATCH v2 2/3] mailbox: exynos: Add support for Exynos850 mailbox

Tudor Ambarus
2026-04-02T08:42:36Z

Hi, Alexey,

On 4/2/26 5:20 AM, Alexey Klimov wrote:
> Exynos850-based platforms support ACPM and has similar workflow
> of communicating with ACPM via mailbox, however mailbox controller
> registers are located at different offsets and writes/reads could be
> different. To distinguish between such different behaviours,
> the registers offsets for Exynos850 and the platform-specific data
> structs are introduced and configuration is described in such structs
> for gs101 and exynos850 based SoCs. Probe routine now selects the
> corresponding platform-specific data via device_get_match_data().
>
> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
> ---
> drivers/mailbox/exynos-mailbox.c | 67 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mailbox.c
> index d2355b128ba4..f9c59c07558a 100644
> --- a/drivers/mailbox/exynos-mailbox.c
> +++ b/drivers/mailbox/exynos-mailbox.c
> @@ -31,14 +31,61 @@
>
> #define EXYNOS_MBOX_CHAN_COUNT HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK)
>
> +#define EXYNOS850_MBOX_MCUCTRL 0x0 /* Mailbox Control Register */
> +#define EXYNOS850_MBOX_INTGR0 0x8 /* Interrupt Generation Register 0 */
> +#define EXYNOS850_MBOX_INTCR0 0x0C /* Interrupt Clear Register 0 */
> +#define EXYNOS850_MBOX_INTMR0 0x10 /* Interrupt Mask Register 0 */
> +#define EXYNOS850_MBOX_INTSR0 0x14 /* Interrupt Status Register 0 */
> +#define EXYNOS850_MBOX_INTMSR0 0x18 /* Interrupt Mask Status Register 0 */
> +#define EXYNOS850_MBOX_INTGR1 0x1C /* Interrupt Generation Register 1 */
> +#define EXYNOS850_MBOX_INTMR1 0x24 /* Interrupt Mask Register 1 */
> +#define EXYNOS850_MBOX_INTSR1 0x28 /* Interrupt Status Register 1 */
> +#define EXYNOS850_MBOX_INTMSR1 0x2C /* Interrupt Mask Status Register 1 */
> +#define EXYNOS850_MBOX_VERSION 0x70

Please consider defining just the registers that are used, to not
pollute the driver. You may drop the unused gs101 definitions too.

> +
> +#define EXYNOS850_MBOX_INTMR1_MASK GENMASK(15, 0)
> +
> +/**
> + * struct exynos_mbox_driver_data - platform-specific mailbox configuration.
> + * @irq_doorbell_offset: offset to the IRQ generation register, doorbell
> + * to APM co-processor.
> + * @irq_doorbell_shift: shift to apply to the value written to IRQ
> + * generation register.
> + * @irq_mask_offset: offset to the IRQ mask register.
> + * @irq_mask_value: value to right to the mask register to mask out
> + * all interrupts.
> + */
> +struct exynos_mbox_driver_data {
> + u16 irq_doorbell_offset;
> + u16 irq_doorbell_shift;
> + u16 irq_mask_offset;
> + u16 irq_mask_value;
> +};
> +
> /**
> * struct exynos_mbox - driver's private data.
> * @regs: mailbox registers base address.
> * @mbox: pointer to the mailbox controller.
> + * @data: pointer to driver platform-specific data.
> */
> struct exynos_mbox {
> void __iomem *regs;
> struct mbox_controller *mbox;
> + const struct exynos_mbox_driver_data *data;
> +};
> +
> +static const struct exynos_mbox_driver_data exynos850_mbox_data = {
> + .irq_doorbell_offset = EXYNOS850_MBOX_INTGR0,
> + .irq_doorbell_shift = 16,
> + .irq_mask_offset = EXYNOS850_MBOX_INTMR1,
> + .irq_mask_value = EXYNOS850_MBOX_INTMR1_MASK,
> +};
> +
> +static const struct exynos_mbox_driver_data exynos_gs101_mbox_data = {
> + .irq_doorbell_offset = EXYNOS_MBOX_INTGR1,
> + .irq_doorbell_shift = 0,
> + .irq_mask_offset = EXYNOS_MBOX_INTMR0,
> + .irq_mask_value = EXYNOS_MBOX_INTMR0_MASK,
> };

I find it strange that the SoCs use different registers. Are you sure you're
using the right direction? i.e. ring the doorbell to APM and not to AP?

>
> static int exynos_mbox_send_data(struct mbox_chan *chan, void *data)
> @@ -57,7 +104,8 @@ static int exynos_mbox_send_data(struct mbox_chan *chan, void *data)
> return -EINVAL;
> }
>
> - writel(BIT(msg->chan_id), exynos_mbox->regs + EXYNOS_MBOX_INTGR1);
> + writel(BIT(msg->chan_id) << exynos_mbox->data->irq_doorbell_shift,
> + exynos_mbox->regs + exynos_mbox->data->irq_doorbell_offset);

Use FIELD_PREP from <linux/bitfield.h> please. You will use a mask instead of
a shift.

I would rename irq_doorbell_offset to intgr. It aligns with the register name
from the datasheet. You won't need to prepend _offset to the name, we already
see it's an offset when doing the writel().

>
> return 0;
> }
> @@ -87,13 +135,21 @@ static struct mbox_chan *exynos_mbox_of_xlate(struct mbox_controller *mbox,
> }
>
> static const struct of_device_id exynos_mbox_match[] = {
> - { .compatible = "google,gs101-mbox" },
> + {
> + .compatible = "google,gs101-mbox",
> + .data = &exynos_gs101_mbox_data
> + },
> + {
> + .compatible = "samsung,exynos850-mbox",
> + .data = &exynos850_mbox_data
> + },
> {},
> };
> MODULE_DEVICE_TABLE(of, exynos_mbox_match);
>
> static int exynos_mbox_probe(struct platform_device *pdev)
> {
> + const struct exynos_mbox_driver_data *data;
> struct device *dev = &pdev->dev;
> struct exynos_mbox *exynos_mbox;
> struct mbox_controller *mbox;
> @@ -122,6 +178,11 @@ static int exynos_mbox_probe(struct platform_device *pdev)
> return dev_err_probe(dev, PTR_ERR(pclk),
> "Failed to enable clock.\n");
>
> + data = device_get_match_data(&pdev->dev);
> + if (!data)
> + return -ENODEV;
> +
> + exynos_mbox->data = data;
> mbox->num_chans = EXYNOS_MBOX_CHAN_COUNT;
> mbox->chans = chans;
> mbox->dev = dev;
> @@ -133,7 +194,7 @@ static int exynos_mbox_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, exynos_mbox);
>
> /* Mask out all interrupts. We support just polling channels for now. */
> - writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0);
> + writel(data->irq_mask_value, exynos_mbox->regs + data->irq_mask_offset);
>

and here I would s/irq_mask_value/intmr_mask and irq_mask_offset/intmr.

Cheers,
ta

> return devm_mbox_controller_register(dev, mbox);
> }
>