From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB2FBC433DB for ; Thu, 4 Mar 2021 00:25:08 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4652664EC0 for ; Thu, 4 Mar 2021 00:25:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4652664EC0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=marcan.st Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:Subject: From:References:Cc:To:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=8VMqyIOrKzmdeE4F4PzB+hz+UD7wUzc1RDpnr/gwQ7M=; b=hbF+wDqZKJUdnrbwmf+XeAhxq FAgvnJIXbtgDJbp701Us26Fw1XRZQu0wnKV9p+OypDegdqK/cHslwni2nwEvAr2wDjKRheVJOJLY7 jFI8/c2ieHh0ULv/7jko/+8skve8miS6iTWXwgsnw6b1v8QV/u2VIadoEDZTcHcPaO2cHuuerluKg 4gig1bTWCmBSj1L3rUPaYsYIE8ji8xg3KY5nzj2lAvk/kJwMYozFmzNESy2ex9lBM+Rc7Ioegj+FU Yz8+keaQQxsSMiRdifZSpuwRQs1l163/aM6yiskTbp4imq5xP4bVag9S9A5HGMRqMLw9gpnsP+TII MZak9EUCg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lHbk1-0078D4-DC; Thu, 04 Mar 2021 00:21:21 +0000 Received: from marcansoft.com ([212.63.210.85] helo=mail.marcansoft.com) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lHVrG-005wEu-6y for linux-arm-kernel@lists.infradead.org; Wed, 03 Mar 2021 18:04:29 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: marcan@marcan.st) by mail.marcansoft.com (Postfix) with ESMTPSA id DFC603FA1B; Wed, 3 Mar 2021 18:04:22 +0000 (UTC) To: Will Deacon Cc: Linux ARM , Marc Zyngier , Mark Rutland , Peter Zijlstra , Boqun Feng , Catalin Marinas References: <90ea3e27-b2ef-41ac-75c7-5f0686603b2a@marcan.st> <20210303153619.GA19247@willie-the-truck> From: Hector Martin Subject: Re: LSE atomic op ordering is weaker than intended? Message-ID: Date: Thu, 4 Mar 2021 03:04:20 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210303153619.GA19247@willie-the-truck> Content-Language: es-ES X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 04/03/2021 00.36, Will Deacon wrote: >> Did I miss something, or is this in fact an issue? > > Both. The -AL atomics are actually special-cased in the > "barrier-ordered-before" relation in the Arm ARM: > > [RW1 is barrier-ordered-before if] > * RW1 appears in program order before an atomic instruction with both > Acquire and Release semantics that appears in program order before > RW2. > > However, that isn't sufficient to order prior accesses with the "load part" > of the RmW and later accesses with the "store part" of the RmW, as you have > observed in your test. I'm aware of some pending proposals in this area of > the architecture, so I'm reluctant to make any changes until that's > bottomed-out, but I'll make a note to chase that up. I had actually seen that part of the spec, and looked at it sideways a few times, but concluded it wasn't giving me the ordering guarantees I was looking for (this was before I wrote the litmus test). You're right, it does nonetheless make it stronger than the mere combination of _acquire and _release semantics. Glad to hear this is something being worked on! I've been giving myself a crash course in memory model minutiae over the past few weeks :) >> (And while I'm talking to the right people: this issue aside, do atomic ops >> on Normal memory create ordering with Device memory ops, or are there no >> guarantees there due to the fact that Normal memory is mapped >> inner-shareable and the ordering guarantees thus do not extend to >> outer-shareable Device accesses? My currenty understanding is the latter, >> but I find the ARM ARM wording hard to conclusively grok here.) > > Outer-shareable is a superset of inner-shareable, but I think this would be > easier with a specific example. I'll go and look at the AIC patch, since > this is all a lot easier to talk about in the context of some real code. > > Which is the latest version I should look at? I'm just about to send a v3 tomorrow, so I'll CC you on that patch (don't bother with v2, this part of the code is changing a lot). That said, it's basically the following two sequences: A: // ...stuff that needs to be ordered prior to the atomic here ret = atomic_fetch_or_release(flags...) if (condition on ret and unrelated stuff) { writel(reg_send, ...) // includes pre-barrier } B: writel_relaxed(reg_ack, ...) dma_wmb() // need a post-barrier atomic_fetch_andnot_acquire(flags...) // ...stuff that needs to be ordered after the atomic here My current understanding is that I cannot drop the dma_wmb() in B and use _relaxed in A() and instead use full-ordered atomic ops, because the atomic ops, operating on normal IS memory, would not make any statements regarding ordering with device OS memory. I need the I/O writes to be ordered with regard to the atomics. -- Hector Martin (marcan@marcan.st) Public Key: https://mrcn.st/pub _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel