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Sun, 24 May 2020 22:30:40 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Sun, 24 May 2020 22:30:40 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Sun, 24 May 2020 22:30:40 -0500 Received: from [10.250.233.85] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04P3UaY4024489; Sun, 24 May 2020 22:30:37 -0500 Subject: Re: [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses To: Rob Herring References: <20200522033631.32574-1-kishon@ti.com> <20200522033631.32574-4-kishon@ti.com> From: Kishon Vijay Abraham I Message-ID: Date: Mon, 25 May 2020 09:00:36 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200524_203103_050794_D230E518 X-CRM114-Status: GOOD ( 15.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lorenzo Pieralisi , Arnd Bergmann , PCI , "linux-kernel@vger.kernel.org" , Tom Joseph , Greg Kroah-Hartman , Bjorn Helgaas , linux-omap , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob, On 5/22/2020 9:24 PM, Rob Herring wrote: > On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I wrote: >> >> Certain platforms like TI's J721E using Cadence PCIe IP can perform only >> 32-bit accesses for reading or writing to Cadence registers. Convert all >> read and write accesses to 32-bit in Cadence PCIe driver in preparation >> for adding PCIe support in TI's J721E SoC. > > Looking more closely I don't think cdns_pcie_ep_assert_intx is okay > with this and never can be given the PCI_COMMAND and PCI_STATUS > registers are in the same word (IIRC, that's the main reason 32-bit > config space accesses are broken). So this isn't going to work at right, PCI_STATUS has write '1' to clear bits and there's a chance that it could be reset while raising legacy interrupt. While this cannot be avoided for TI's J721E, other platforms doesn't have to have this limitation. > least for EP accesses. And maybe you need a custom .raise_irq() hook > to minimize any problems (such as making the RMW atomic at least from > the endpoint's perspective). This is to make sure EP doesn't update in-consistent state when RC is updating the PCI_STATUS register? Since this involves two different systems, how do we make this atomic? Thanks Kishon _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel