From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45FDAC48BF8 for ; Thu, 22 Feb 2024 11:31:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DsYMbuNQFFnKwHEY5kMGmKh+bY6ssHAcpvaWc9Ot7cE=; b=dXC3RzcUNlAnZk gVgoo1qrYQ5UItvvnBrrWsBOvT5+zRPsFD38D+o6y0S43l2CdrMU5t2xLksPNfNqu5buyuYkyxX0Z xsft7R5aGABbylGoG18BWGAMkdSk2hS8YR0w6vwxpdhYDTnMcOSK1h907cuaoWvSAPrtg5uwuZ+l6 rgwkksdhrF76ViBWbwuzBqu3b/+UNXFmrRUwTHMGeFisd1yus1MFIep8FDgEeqeYLaAi6T+EoR8cW ZfnblYHchHtR2phloqu3LDGzp5C4hNDnadCihWDDbDuLYdNOE6VkTm/70yq0XbFtXW9+NfVmMjl8l BfffnR6WeeO5xGHfqcVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rd7Ia-00000004e6X-3Fdx; Thu, 22 Feb 2024 11:31:32 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rd7IX-00000004e4J-1Shl for linux-arm-kernel@lists.infradead.org; Thu, 22 Feb 2024 11:31:31 +0000 Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4TgWD66hp6z1vv47; Thu, 22 Feb 2024 19:30:46 +0800 (CST) Received: from dggems704-chm.china.huawei.com (unknown [10.3.19.181]) by mail.maildlp.com (Postfix) with ESMTPS id 8AF6E18002F; Thu, 22 Feb 2024 19:31:21 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (7.191.163.240) by dggems704-chm.china.huawei.com (10.3.19.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 22 Feb 2024 19:31:20 +0800 Received: from lhrpeml500005.china.huawei.com ([7.191.163.240]) by lhrpeml500005.china.huawei.com ([7.191.163.240]) with mapi id 15.01.2507.035; Thu, 22 Feb 2024 11:31:18 +0000 From: Shameerali Kolothum Thodi To: Joao Martins CC: "joro@8bytes.org" , "jgg@nvidia.com" , "kevin.tian@intel.com" , "nicolinc@nvidia.com" , "iommu@lists.linux.dev" , "mshavit@google.com" , "robin.murphy@arm.com" , "will@kernel.org" , jiangkunkun , zhukeqian , Linuxarm , "linux-arm-kernel@lists.infradead.org" Subject: RE: [PATCH v2 3/4] iommu/arm-smmu-v3: Add support for dirty tracking in domain alloc Thread-Topic: [PATCH v2 3/4] iommu/arm-smmu-v3: Add support for dirty tracking in domain alloc Thread-Index: AQHaZXTSExgSw/uTxUa44V9Mknrnh7EWMsuAgAAGflA= Date: Thu, 22 Feb 2024 11:31:18 +0000 Message-ID: References: <20240222094923.33104-1-shameerali.kolothum.thodi@huawei.com> <20240222094923.33104-4-shameerali.kolothum.thodi@huawei.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.28] MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240222_033129_771357_5C12C2CA X-CRM114-Status: GOOD ( 29.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Joao Martins > Sent: Thursday, February 22, 2024 11:04 AM > To: Shameerali Kolothum Thodi > Cc: joro@8bytes.org; jgg@nvidia.com; kevin.tian@intel.com; > nicolinc@nvidia.com; iommu@lists.linux.dev; mshavit@google.com; > robin.murphy@arm.com; will@kernel.org; jiangkunkun > ; zhukeqian ; > Linuxarm ; linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH v2 3/4] iommu/arm-smmu-v3: Add support for dirty > tracking in domain alloc > > On 22/02/2024 09:49, Shameer Kolothum wrote: > > From: Joao Martins > > > > This provides all the infrastructure to enable dirty tracking if the > > hardware has the capability and domain alloc request for it. > > > > Please note, we still report no support for IOMMU_CAP_DIRTY_TRACKING > > as it will finally be enabled in a subsequent patch. > > > > Signed-off-by: Joao Martins > > Signed-off-by: Shameer Kolothum > > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 95 > ++++++++++++++++----- > > include/linux/io-pgtable.h | 4 + > > 2 files changed, 77 insertions(+), 22 deletions(-) > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index bd30739e3588..058bbb0dbe2e 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -43,6 +43,7 @@ MODULE_PARM_DESC(disable_msipolling, > > "Disable MSI-based polling for CMD_SYNC completion."); > > > > static struct iommu_ops arm_smmu_ops; > > +static struct iommu_dirty_ops arm_smmu_dirty_ops; > > > > enum arm_smmu_msi_index { > > EVTQ_MSI_INDEX, > > @@ -86,7 +87,8 @@ static struct arm_smmu_option_prop > > arm_smmu_options[] = { > > > > static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device > > *smmu); static int arm_smmu_domain_finalise(struct arm_smmu_domain > *smmu_domain, > > - struct arm_smmu_device *smmu); > > + struct arm_smmu_device *smmu, > > + bool enable_dirty); > > static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master); > > static void arm_smmu_tlb_inv_all_s2(struct arm_smmu_domain > > *smmu_domain); > > > > @@ -2378,7 +2380,7 @@ static struct iommu_domain > *arm_smmu_domain_alloc_paging(struct device *dev) > > struct arm_smmu_master *master = > dev_iommu_priv_get(dev); > > int ret; > > > > - ret = arm_smmu_domain_finalise(smmu_domain, master- > >smmu); > > + ret = arm_smmu_domain_finalise(smmu_domain, master- > >smmu, false); > > if (ret) { > > kfree(smmu_domain); > > return ERR_PTR(ret); > > @@ -2445,10 +2447,11 @@ static void arm_smmu_domain_free(struct > > iommu_domain *domain) } > > > > static int arm_smmu_domain_finalise(struct arm_smmu_domain > *smmu_domain, > > - struct arm_smmu_device *smmu) > > + struct arm_smmu_device *smmu, > > + bool enable_dirty) > > { > > int ret; > > - unsigned long ias, oas; > > + unsigned long ias; > > enum io_pgtable_fmt fmt; > > struct io_pgtable_cfg pgtbl_cfg; > > struct io_pgtable_ops *pgtbl_ops; > > @@ -2459,31 +2462,31 @@ static int arm_smmu_domain_finalise(struct > arm_smmu_domain *smmu_domain, > > if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) > > smmu_domain->stage = ARM_SMMU_DOMAIN_S1; > > > > + pgtbl_cfg = (struct io_pgtable_cfg) { > > + .pgsize_bitmap = smmu->pgsize_bitmap, > > + .coherent_walk = smmu->features & > ARM_SMMU_FEAT_COHERENCY, > > + .tlb = &arm_smmu_flush_ops, > > + .iommu_dev = smmu->dev, > > + }; > > + > > switch (smmu_domain->stage) { > > case ARM_SMMU_DOMAIN_S1: > > ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; > > - ias = min_t(unsigned long, ias, VA_BITS); > > - oas = smmu->ias; > > + pgtbl_cfg.ias = min_t(unsigned long, ias, VA_BITS); > > + pgtbl_cfg.oas = smmu->ias; > > + if (enable_dirty) > > + pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_HD; > > fmt = ARM_64_LPAE_S1; > > break; > > case ARM_SMMU_DOMAIN_S2: > > - ias = smmu->ias; > > - oas = smmu->oas; > > + pgtbl_cfg.ias = smmu->ias; > > + pgtbl_cfg.oas = smmu->oas; > > fmt = ARM_64_LPAE_S2; > > break; > > default: > > return -EINVAL; > > } > > > > - pgtbl_cfg = (struct io_pgtable_cfg) { > > - .pgsize_bitmap = smmu->pgsize_bitmap, > > - .ias = ias, > > - .oas = oas, > > - .coherent_walk = smmu->features & > ARM_SMMU_FEAT_COHERENCY, > > - .tlb = &arm_smmu_flush_ops, > > - .iommu_dev = smmu->dev, > > - }; > > - > > pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); > > if (!pgtbl_ops) > > return -ENOMEM; > > @@ -2491,7 +2494,8 @@ static int arm_smmu_domain_finalise(struct > arm_smmu_domain *smmu_domain, > > smmu_domain->domain.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; > > smmu_domain->domain.geometry.aperture_end = (1UL << > pgtbl_cfg.ias) - 1; > > smmu_domain->domain.geometry.force_aperture = true; > > - > > + if (enable_dirty && smmu_domain->stage == > ARM_SMMU_DOMAIN_S1) > > + smmu_domain->domain.dirty_ops = > &arm_smmu_dirty_ops; > > ret = arm_smmu_domain_alloc_id(smmu, smmu_domain); > > if (ret < 0) { > > free_io_pgtable_ops(pgtbl_ops); > > @@ -2811,7 +2815,7 @@ static int arm_smmu_attach_dev(struct > iommu_domain *domain, struct device *dev) > > mutex_lock(&smmu_domain->init_mutex); > > > > if (!smmu_domain->smmu) { > > - ret = arm_smmu_domain_finalise(smmu_domain, smmu); > > + ret = arm_smmu_domain_finalise(smmu_domain, smmu, > false); > > } else if (smmu_domain->smmu != smmu) > > ret = -EINVAL; > > > > > I think we are missing the domain attach_dev check for dirty tracking. > > Something like: > > if (domain->dirty_ops && !arm_smmu_dbm_capable(smmu)) > return -EINVAL; > > But that helper is only introduced in the last patch, so maybe: > > if (domain->dirty_ops && > !device_iommu_capable(dev, IOMMU_CAP_DIRTY_TRACKING)) > return -EINVAL; Ok. But do we really need to check this in attach()? As dirty_ops are added only if it is requested in alloc_user() and there we return err when hardware doesn't have the capability. So not sure how this matters in attach() path. May be I am missing something. Thanks, Shameer _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel