* [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells
@ 2022-11-26 22:47 Marek Vasut
2022-11-26 22:47 ` [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Marek Vasut
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-26 22:47 UTC (permalink / raw)
To: linux-pm, linux-arm-kernel
Cc: Marek Vasut, Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Li Jun, Lucas Stach,
Markus Niebel, NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values from OCOTP. Document optional phandle to OCOTP nvmem
provider.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
.../devicetree/bindings/thermal/imx8mm-thermal.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml
index 89c54e08ee61b..b90726229ac9c 100644
--- a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml
@@ -32,6 +32,13 @@ properties:
clocks:
maxItems: 1
+ nvmem-cells:
+ maxItems: 1
+ description: Phandle to the calibration data provided by ocotp
+
+ nvmem-cell-names:
+ const: calib
+
"#thermal-sensor-cells":
description: |
Number of cells required to uniquely identify the thermal
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address
2022-11-26 22:47 [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut
@ 2022-11-26 22:47 ` Marek Vasut
2022-11-28 2:16 ` Peng Fan
2022-11-26 22:47 ` [PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation Marek Vasut
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Marek Vasut @ 2022-11-26 22:47 UTC (permalink / raw)
To: linux-pm, linux-arm-kernel
Cc: Marek Vasut, Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Li Jun, Lucas Stach,
Markus Niebel, NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree
Align the SoC unique ID DT node unit address with its reg property.
Fixes: cbff23797fa1 ("arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID")
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 0c97aca8db6b6..423cb36cbcd53 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -563,7 +563,7 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mm_uid: unique-id@410 {
+ imx8mm_uid: unique-id@4 {
reg = <0x4 0x8>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 9b3a9e1384ae9..312e3abc35ea8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -564,7 +564,7 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mn_uid: unique-id@410 {
+ imx8mn_uid: unique-id@4 {
reg = <0x4 0x8>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index f18cf611f778e..c9459ed21b243 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -426,7 +426,7 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mp_uid: unique-id@420 {
+ imx8mp_uid: unique-id@8 {
reg = <0x8 0x8>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 5246b44a37d4a..2b6d3f4ff5d93 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -593,7 +593,7 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mq_uid: soc-uid@410 {
+ imx8mq_uid: soc-uid@4 {
reg = <0x4 0x8>;
};
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation
2022-11-26 22:47 [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut
2022-11-26 22:47 ` [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Marek Vasut
@ 2022-11-26 22:47 ` Marek Vasut
2022-11-28 2:18 ` Peng Fan
2022-11-26 22:47 ` [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Marek Vasut
` (2 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Marek Vasut @ 2022-11-26 22:47 UTC (permalink / raw)
To: linux-pm, linux-arm-kernel
Cc: Marek Vasut, Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Li Jun, Lucas Stach,
Markus Niebel, NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree
The mapping from OCOTP reg DT property to Fusemap Descriptions Table in
the datasheet is often unclear. Add a comment to make it easier to find
out how it works. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 ++++++++++++++++---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 ++++++++++++++++---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 21 +++++++++++++++++----
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 ++++++++++++++++---
4 files changed, 65 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 423cb36cbcd53..513c2de0caa15 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -563,15 +563,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mm_uid: unique-id@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 312e3abc35ea8..068f599cdf757 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -564,15 +564,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mn_uid: unique-id@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c9459ed21b243..ddcd5e23ba47d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -426,19 +426,32 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mp_uid: unique-id@8 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x8 0x8> describes fuses 0x420 and
+ * 0x430).
+ */
+ imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
reg = <0x8 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- eth_mac1: mac-address@90 {
+ eth_mac1: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
- eth_mac2: mac-address@96 {
+ eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 2b6d3f4ff5d93..8a2ec90b493d9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -593,15 +593,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mq_uid: soc-uid@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
2022-11-26 22:47 [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut
2022-11-26 22:47 ` [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Marek Vasut
2022-11-26 22:47 ` [PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation Marek Vasut
@ 2022-11-26 22:47 ` Marek Vasut
2022-11-28 2:29 ` Peng Fan
2022-11-28 8:34 ` Alexander Stein
2022-11-26 22:47 ` [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP Marek Vasut
2022-11-27 12:33 ` [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Krzysztof Kozlowski
4 siblings, 2 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-26 22:47 UTC (permalink / raw)
To: linux-pm, linux-arm-kernel
Cc: Marek Vasut, Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Li Jun, Lucas Stach,
Markus Niebel, NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
3 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 513c2de0caa15..0cd7fff47c44d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -496,6 +496,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 068f599cdf757..5eef9b274edde 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -498,6 +498,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index ddcd5e23ba47d..0173e394ad4d8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -380,6 +380,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mp-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <1>;
};
@@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */
eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
+
+ tmu_calib: calib@264 { /* 0xd90-0xdc0 */
+ reg = <0x264 0x10>;
+ };
};
anatop: clock-controller@30360000 {
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP
2022-11-26 22:47 [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut
` (2 preceding siblings ...)
2022-11-26 22:47 ` [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Marek Vasut
@ 2022-11-26 22:47 ` Marek Vasut
2022-11-28 2:58 ` Peng Fan
2022-11-27 12:33 ` [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Krzysztof Kozlowski
4 siblings, 1 reply; 12+ messages in thread
From: Marek Vasut @ 2022-11-26 22:47 UTC (permalink / raw)
To: linux-pm, linux-arm-kernel
Cc: Marek Vasut, Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Li Jun, Lucas Stach,
Markus Niebel, NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add support for reading the OCOTP calibration
data and programming those into the TMU hardware.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4,
the programming differs in each case.
Based on U-Boot commits:
70487ff386c ("imx8mm: Load fuse for TMU TCALIV and TASR")
ebb9aab318b ("imx: load calibration parameters from fuse for i.MX8MP")
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
drivers/thermal/imx8mm_thermal.c | 163 +++++++++++++++++++++++++++++++
1 file changed, 163 insertions(+)
diff --git a/drivers/thermal/imx8mm_thermal.c b/drivers/thermal/imx8mm_thermal.c
index e2c2673025a7a..da09c00ac663a 100644
--- a/drivers/thermal/imx8mm_thermal.c
+++ b/drivers/thermal/imx8mm_thermal.c
@@ -10,6 +10,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
@@ -20,6 +21,22 @@
#define TER 0x0 /* TMU enable */
#define TPS 0x4
#define TRITSR 0x20 /* TMU immediate temp */
+/* TMU calibration data registers */
+#define TASR 0x28
+#define TASR_BUF_SLOPE_MASK GENMASK(19, 16)
+#define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */
+#define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */
+#define TCALIV(n) (0x30 + ((n) * 4))
+#define TCALIV_EN BIT(31)
+#define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 */
+#define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */
+#define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 */
+#define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 */
+#define TRIM 0x3c
+#define TRIM_BJT_CUR_MASK GENMASK(23, 20)
+#define TRIM_BGR_MASK GENMASK(31, 28)
+#define TRIM_VLSB_MASK GENMASK(15, 12)
+#define TRIM_EN_CH BIT(7)
#define TER_ADC_PD BIT(30)
#define TER_EN BIT(31)
@@ -32,6 +49,25 @@
#define SIGN_BIT BIT(7)
#define TEMP_VAL_MASK GENMASK(6, 0)
+/* TMU OCOTP calibration data bitfields */
+#define ANA0_EN BIT(25)
+#define ANA0_BUF_VREF_MASK GENMASK(24, 20)
+#define ANA0_BUF_SLOPE_MASK GENMASK(19, 16)
+#define ANA0_HR_MASK GENMASK(15, 8)
+#define ANA0_RT_MASK GENMASK(7, 0)
+#define TRIM2_VLSB_MASK GENMASK(23, 20)
+#define TRIM2_BGR_MASK GENMASK(19, 16)
+#define TRIM2_BJT_CUR_MASK GENMASK(15, 12)
+#define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8)
+#define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6)
+#define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28)
+#define TRIM3_TCA40_0_MASK GENMASK(27, 16)
+#define TRIM4_TCA40_1_MASK GENMASK(31, 20)
+#define TRIM4_TCA105_0_MASK GENMASK(19, 8)
+#define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0)
+#define TRIM5_TCA105_1_MASK GENMASK(23, 12)
+#define TRIM5_TCA25_1_MASK GENMASK(11, 0)
+
#define VER1_TEMP_LOW_LIMIT 10000
#define VER2_TEMP_LOW_LIMIT -40000
#define VER2_TEMP_HIGH_LIMIT 125000
@@ -128,6 +164,129 @@ static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu)
writel_relaxed(val, tmu->base + TPS);
}
+static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev,
+ struct imx8mm_tmu *tmu)
+{
+ struct device *dev = &pdev->dev;
+ u32 ana0;
+ int ret;
+
+ ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0);
+ if (ret) {
+ dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n", ret);
+ return ret;
+ }
+
+ writel(FIELD_PREP(TASR_BUF_VREF_MASK,
+ FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) |
+ FIELD_PREP(TASR_BUF_SLOPE_MASK,
+ FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)),
+ tmu->base + TASR);
+
+ writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, ana0)) |
+ FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0)) |
+ ((ana0 & ANA0_EN) ? TCALIV_EN : 0),
+ tmu->base + TCALIV(0));
+
+ return 0;
+}
+
+static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev,
+ struct imx8mm_tmu *tmu)
+{
+ struct device *dev = &pdev->dev;
+ struct nvmem_cell *cell;
+ u32 trim[4] = { 0 };
+ size_t len;
+ void *buf;
+
+ cell = nvmem_cell_get(dev, "calib");
+ if (IS_ERR(cell))
+ return PTR_ERR(cell);
+
+ buf = nvmem_cell_read(cell, &len);
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf))
+ return PTR_ERR(buf);
+
+ memcpy(trim, buf, min(len, sizeof(trim)));
+ kfree(buf);
+
+ if (len != 16) {
+ dev_err(dev,
+ "OCOTP nvmem cell length is %ld, must be 16.\n", len);
+ return -EINVAL;
+ }
+
+ /* Blank sample hardware */
+ if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) {
+ /* Use a default 25C binary codes */
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
+ tmu->base + TCALIV(0));
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
+ tmu->base + TCALIV(1));
+ return 0;
+ }
+
+ writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK,
+ FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) |
+ FIELD_PREP(TASR_BUF_SLOPE_MASK,
+ FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])),
+ tmu->base + TASR);
+
+ writel(FIELD_PREP(TRIM_BJT_CUR_MASK,
+ FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) |
+ FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK, trim[0])) |
+ FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK, trim[0])) |
+ TRIM_EN_CH,
+ tmu->base + TRIM);
+
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
+ FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) |
+ (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) << 4)) |
+ FIELD_PREP(TCALIV_SNSR105C_MASK,
+ FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])),
+ tmu->base + TCALIV(0));
+
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
+ FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) |
+ FIELD_PREP(TCALIV_SNSR105C_MASK,
+ FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])),
+ tmu->base + TCALIV(1));
+
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
+ FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) |
+ FIELD_PREP(TCALIV_SNSR105C_MASK,
+ FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])),
+ tmu->base + TCALIV(2));
+
+ return 0;
+}
+
+static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev,
+ struct imx8mm_tmu *tmu)
+{
+ struct device *dev = &pdev->dev;
+
+ /*
+ * Lack of calibration data OCOTP reference is not considered
+ * fatal to retain compatibility with old DTs. It is however
+ * strongly recommended to update such old DTs to get correct
+ * temperature compensation values for each SoC.
+ */
+ if (!of_find_property(pdev->dev.of_node, "nvmem-cells", NULL)) {
+ dev_warn(dev,
+ "No OCOTP nvmem reference found, SoC-specific calibration not loaded. Please update your DT.\n");
+ return 0;
+ }
+
+ if (tmu->socdata->version == TMU_VER1)
+ return imx8mm_tmu_probe_set_calib_v1(pdev, tmu);
+
+ return imx8mm_tmu_probe_set_calib_v2(pdev, tmu);
+}
+
static int imx8mm_tmu_probe(struct platform_device *pdev)
{
const struct thermal_soc_data *data;
@@ -180,6 +339,10 @@ static int imx8mm_tmu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, tmu);
+ ret = imx8mm_tmu_probe_set_calib(pdev, tmu);
+ if (ret)
+ goto disable_clk;
+
/* enable all the probes for V2 TMU */
if (tmu->socdata->version == TMU_VER2)
imx8mm_tmu_probe_sel_all(tmu);
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells
2022-11-26 22:47 [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut
` (3 preceding siblings ...)
2022-11-26 22:47 ` [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP Marek Vasut
@ 2022-11-27 12:33 ` Krzysztof Kozlowski
4 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-27 12:33 UTC (permalink / raw)
To: Marek Vasut, linux-pm, linux-arm-kernel
Cc: Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Li Jun, Lucas Stach,
Markus Niebel, NXP Linux Team, Peng Fan, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree
On 26/11/2022 23:47, Marek Vasut wrote:
> The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
> calibration values from OCOTP. Document optional phandle to OCOTP nvmem
> provider.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address
2022-11-26 22:47 ` [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Marek Vasut
@ 2022-11-28 2:16 ` Peng Fan
0 siblings, 0 replies; 12+ messages in thread
From: Peng Fan @ 2022-11-28 2:16 UTC (permalink / raw)
To: Marek Vasut, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Jun Li, Lucas Stach,
Markus Niebel, dl-linux-imx, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree@vger.kernel.org
> Subject: [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address
>
> Align the SoC unique ID DT node unit address with its reg property.
>
> Fixes: cbff23797fa1 ("arm64: dts: imx8m: add NVMEM provider and consumer
> to read soc unique ID")
> Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Alice Guo <alice.guo@nxp.com>
> Cc: Amit Kucheria <amitk@kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Li Jun <jun.li@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Rafael J. Wysocki <rafael@kernel.org>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Zhang Rui <rui.zhang@intel.com>
> Cc: devicetree@vger.kernel.org
> To: linux-pm@vger.kernel.org
> To: linux-arm-kernel@lists.infradead.org
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 +-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 0c97aca8db6b6..423cb36cbcd53 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -563,7 +563,7 @@ ocotp: efuse@30350000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mm_uid: unique-id@410 {
> + imx8mm_uid: unique-id@4 {
> reg = <0x4 0x8>;
> };
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9b3a9e1384ae9..312e3abc35ea8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -564,7 +564,7 @@ ocotp: efuse@30350000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mn_uid: unique-id@410 {
> + imx8mn_uid: unique-id@4 {
> reg = <0x4 0x8>;
> };
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index f18cf611f778e..c9459ed21b243 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -426,7 +426,7 @@ ocotp: efuse@30350000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mp_uid: unique-id@420 {
> + imx8mp_uid: unique-id@8 {
> reg = <0x8 0x8>;
> };
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 5246b44a37d4a..2b6d3f4ff5d93 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -593,7 +593,7 @@ ocotp: efuse@30350000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mq_uid: soc-uid@410 {
> + imx8mq_uid: soc-uid@4 {
> reg = <0x4 0x8>;
> };
>
> --
> 2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation
2022-11-26 22:47 ` [PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation Marek Vasut
@ 2022-11-28 2:18 ` Peng Fan
0 siblings, 0 replies; 12+ messages in thread
From: Peng Fan @ 2022-11-28 2:18 UTC (permalink / raw)
To: Marek Vasut, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Jun Li, Lucas Stach,
Markus Niebel, dl-linux-imx, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree@vger.kernel.org
> Subject: [PATCH 3/5] arm64: dts: imx8m: Document the fuse address
> calculation
>
> The mapping from OCOTP reg DT property to Fusemap Descriptions Table in
> the datasheet is often unclear. Add a comment to make it easier to find out
> how it works. No functional change.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Alice Guo <alice.guo@nxp.com>
> Cc: Amit Kucheria <amitk@kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Li Jun <jun.li@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Rafael J. Wysocki <rafael@kernel.org>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Zhang Rui <rui.zhang@intel.com>
> Cc: devicetree@vger.kernel.org
> To: linux-pm@vger.kernel.org
> To: linux-arm-kernel@lists.infradead.org
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 ++++++++++++++++---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 ++++++++++++++++---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 21 +++++++++++++++++----
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 ++++++++++++++++---
> 4 files changed, 65 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 423cb36cbcd53..513c2de0caa15 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -563,15 +563,28 @@ ocotp: efuse@30350000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mm_uid: unique-id@4 {
> + /*
> + * The register address below maps to the
> MX8M
> + * Fusemap Description Table entries this way.
> + * Assuming
> + * reg = <ADDR SIZE>;
> + * then
> + * Fuse Address = (ADDR * 4) + 0x400
> + * Note that if SIZE is greater than 4, then
> + * each subsequent fuse is located at offset
> + * +0x10 in Fusemap Description Table (e.g.
> + * reg = <0x4 0x8> describes fuses 0x410 and
> + * 0x420).
> + */
> + imx8mm_uid: unique-id@4 { /* 0x410-0x420
> */
> reg = <0x4 0x8>;
> };
>
> - cpu_speed_grade: speed-grade@10 {
> + cpu_speed_grade: speed-grade@10 { /*
> 0x440 */
> reg = <0x10 4>;
> };
>
> - fec_mac_address: mac-address@90 {
> + fec_mac_address: mac-address@90 { /*
> 0x640 */
> reg = <0x90 6>;
> };
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 312e3abc35ea8..068f599cdf757 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -564,15 +564,28 @@ ocotp: efuse@30350000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mn_uid: unique-id@4 {
> + /*
> + * The register address below maps to the
> MX8M
> + * Fusemap Description Table entries this way.
> + * Assuming
> + * reg = <ADDR SIZE>;
> + * then
> + * Fuse Address = (ADDR * 4) + 0x400
> + * Note that if SIZE is greater than 4, then
> + * each subsequent fuse is located at offset
> + * +0x10 in Fusemap Description Table (e.g.
> + * reg = <0x4 0x8> describes fuses 0x410 and
> + * 0x420).
> + */
> + imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
> reg = <0x4 0x8>;
> };
>
> - cpu_speed_grade: speed-grade@10 {
> + cpu_speed_grade: speed-grade@10 { /*
> 0x440 */
> reg = <0x10 4>;
> };
>
> - fec_mac_address: mac-address@90 {
> + fec_mac_address: mac-address@90 { /*
> 0x640 */
> reg = <0x90 6>;
> };
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index c9459ed21b243..ddcd5e23ba47d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -426,19 +426,32 @@ ocotp: efuse@30350000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mp_uid: unique-id@8 {
> + /*
> + * The register address below maps to the
> MX8M
> + * Fusemap Description Table entries this way.
> + * Assuming
> + * reg = <ADDR SIZE>;
> + * then
> + * Fuse Address = (ADDR * 4) + 0x400
> + * Note that if SIZE is greater than 4, then
> + * each subsequent fuse is located at offset
> + * +0x10 in Fusemap Description Table (e.g.
> + * reg = <0x8 0x8> describes fuses 0x420 and
> + * 0x430).
> + */
> + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
> reg = <0x8 0x8>;
> };
>
> - cpu_speed_grade: speed-grade@10 {
> + cpu_speed_grade: speed-grade@10 { /*
> 0x440 */
> reg = <0x10 4>;
> };
>
> - eth_mac1: mac-address@90 {
> + eth_mac1: mac-address@90 { /* 0x640 */
> reg = <0x90 6>;
> };
>
> - eth_mac2: mac-address@96 {
> + eth_mac2: mac-address@96 { /* 0x658 */
> reg = <0x96 6>;
> };
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 2b6d3f4ff5d93..8a2ec90b493d9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -593,15 +593,28 @@ ocotp: efuse@30350000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mq_uid: soc-uid@4 {
> + /*
> + * The register address below maps to the
> MX8M
> + * Fusemap Description Table entries this way.
> + * Assuming
> + * reg = <ADDR SIZE>;
> + * then
> + * Fuse Address = (ADDR * 4) + 0x400
> + * Note that if SIZE is greater than 4, then
> + * each subsequent fuse is located at offset
> + * +0x10 in Fusemap Description Table (e.g.
> + * reg = <0x4 0x8> describes fuses 0x410 and
> + * 0x420).
> + */
> + imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
> reg = <0x4 0x8>;
> };
>
> - cpu_speed_grade: speed-grade@10 {
> + cpu_speed_grade: speed-grade@10 { /*
> 0x440 */
> reg = <0x10 4>;
> };
>
> - fec_mac_address: mac-address@90 {
> + fec_mac_address: mac-address@90 { /*
> 0x640 */
> reg = <0x90 6>;
> };
> };
> --
> 2.35.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
2022-11-26 22:47 ` [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Marek Vasut
@ 2022-11-28 2:29 ` Peng Fan
2022-11-28 8:34 ` Alexander Stein
1 sibling, 0 replies; 12+ messages in thread
From: Peng Fan @ 2022-11-28 2:29 UTC (permalink / raw)
To: Marek Vasut, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Jun Li, Lucas Stach,
Markus Niebel, dl-linux-imx, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree@vger.kernel.org
> Subject: [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data
> in OCOTP
>
> The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
> calibration values in OCOTP. Add the OCOTP calibration values phandle so the
> TMU driver can perform this programming.
>
> The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2
> uses 4.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Alice Guo <alice.guo@nxp.com>
> Cc: Amit Kucheria <amitk@kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Li Jun <jun.li@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Rafael J. Wysocki <rafael@kernel.org>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Zhang Rui <rui.zhang@intel.com>
> Cc: devicetree@vger.kernel.org
> To: linux-pm@vger.kernel.org
> To: linux-arm-kernel@lists.infradead.org
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
> 3 files changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 513c2de0caa15..0cd7fff47c44d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -496,6 +496,8 @@ tmu: tmu@30260000 {
> compatible = "fsl,imx8mm-tmu";
> reg = <0x30260000 0x10000>;
> clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
> + nvmem-cells = <&tmu_calib>;
> + nvmem-cell-names = "calib";
> #thermal-sensor-cells = <0>;
> };
>
> @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
> reg = <0x10 4>;
> };
>
> + tmu_calib: calib@3c { /* 0x4f0 */
> + reg = <0x3c 4>;
> + };
> +
> fec_mac_address: mac-address@90 { /*
> 0x640 */
> reg = <0x90 6>;
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 068f599cdf757..5eef9b274edde 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -498,6 +498,8 @@ tmu: tmu@30260000 {
> compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-
> tmu";
> reg = <0x30260000 0x10000>;
> clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
> + nvmem-cells = <&tmu_calib>;
> + nvmem-cell-names = "calib";
> #thermal-sensor-cells = <0>;
> };
>
> @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
> reg = <0x10 4>;
> };
>
> + tmu_calib: calib@3c { /* 0x4f0 */
> + reg = <0x3c 4>;
> + };
> +
> fec_mac_address: mac-address@90 { /*
> 0x640 */
> reg = <0x90 6>;
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index ddcd5e23ba47d..0173e394ad4d8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -380,6 +380,8 @@ tmu: tmu@30260000 {
> compatible = "fsl,imx8mp-tmu";
> reg = <0x30260000 0x10000>;
> clocks = <&clk
> IMX8MP_CLK_TSENSOR_ROOT>;
> + nvmem-cells = <&tmu_calib>;
> + nvmem-cell-names = "calib";
> #thermal-sensor-cells = <1>;
> };
>
> @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */
> eth_mac2: mac-address@96 { /* 0x658 */
> reg = <0x96 6>;
> };
> +
> + tmu_calib: calib@264 { /* 0xd90-0xdc0 */
> + reg = <0x264 0x10>;
> + };
> };
>
> anatop: clock-controller@30360000 {
> --
> 2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP
2022-11-26 22:47 ` [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP Marek Vasut
@ 2022-11-28 2:58 ` Peng Fan
0 siblings, 0 replies; 12+ messages in thread
From: Peng Fan @ 2022-11-28 2:58 UTC (permalink / raw)
To: Marek Vasut, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Adam Ford, Alice Guo, Amit Kucheria, Daniel Lezcano,
Fabio Estevam, Krzysztof Kozlowski, Jun Li, Lucas Stach,
Markus Niebel, dl-linux-imx, Pengutronix Kernel Team,
Rafael J . Wysocki, Richard Cochran, Rob Herring, Sascha Hauer,
Shawn Guo, Zhang Rui, devicetree@vger.kernel.org
> Subject: [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration
> data from OCOTP
>
> The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
> calibration values in OCOTP. Add support for reading the OCOTP calibration
> data and programming those into the TMU hardware.
>
> The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2
> uses 4, the programming differs in each case.
>
> Based on U-Boot commits:
> 70487ff386c ("imx8mm: Load fuse for TMU TCALIV and TASR") ebb9aab318b
> ("imx: load calibration parameters from fuse for i.MX8MP")
>
> Signed-off-by: Marek Vasut <marex@denx.de>
Looks good to me
Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Alice Guo <alice.guo@nxp.com>
> Cc: Amit Kucheria <amitk@kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Li Jun <jun.li@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Rafael J. Wysocki <rafael@kernel.org>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Zhang Rui <rui.zhang@intel.com>
> Cc: devicetree@vger.kernel.org
> To: linux-pm@vger.kernel.org
> To: linux-arm-kernel@lists.infradead.org
> ---
> drivers/thermal/imx8mm_thermal.c | 163
> +++++++++++++++++++++++++++++++
> 1 file changed, 163 insertions(+)
>
> diff --git a/drivers/thermal/imx8mm_thermal.c
> b/drivers/thermal/imx8mm_thermal.c
> index e2c2673025a7a..da09c00ac663a 100644
> --- a/drivers/thermal/imx8mm_thermal.c
> +++ b/drivers/thermal/imx8mm_thermal.c
> @@ -10,6 +10,7 @@
> #include <linux/err.h>
> #include <linux/io.h>
> #include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> @@ -20,6 +21,22 @@
> #define TER 0x0 /* TMU enable */
> #define TPS 0x4
> #define TRITSR 0x20 /* TMU immediate temp */
> +/* TMU calibration data registers */
> +#define TASR 0x28
> +#define TASR_BUF_SLOPE_MASK GENMASK(19, 16)
> +#define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */
> +#define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */
> +#define TCALIV(n) (0x30 + ((n) * 4))
> +#define TCALIV_EN BIT(31)
> +#define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1
> */
> +#define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */
> +#define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2
> */
> +#define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2
> */
> +#define TRIM 0x3c
> +#define TRIM_BJT_CUR_MASK GENMASK(23, 20)
> +#define TRIM_BGR_MASK GENMASK(31, 28)
> +#define TRIM_VLSB_MASK GENMASK(15, 12)
> +#define TRIM_EN_CH BIT(7)
>
> #define TER_ADC_PD BIT(30)
> #define TER_EN BIT(31)
> @@ -32,6 +49,25 @@
> #define SIGN_BIT BIT(7)
> #define TEMP_VAL_MASK GENMASK(6, 0)
>
> +/* TMU OCOTP calibration data bitfields */
> +#define ANA0_EN BIT(25)
> +#define ANA0_BUF_VREF_MASK GENMASK(24, 20)
> +#define ANA0_BUF_SLOPE_MASK GENMASK(19, 16)
> +#define ANA0_HR_MASK GENMASK(15, 8)
> +#define ANA0_RT_MASK GENMASK(7, 0)
> +#define TRIM2_VLSB_MASK GENMASK(23, 20)
> +#define TRIM2_BGR_MASK GENMASK(19, 16)
> +#define TRIM2_BJT_CUR_MASK GENMASK(15, 12)
> +#define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8)
> +#define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6)
> +#define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28)
> +#define TRIM3_TCA40_0_MASK GENMASK(27, 16)
> +#define TRIM4_TCA40_1_MASK GENMASK(31, 20)
> +#define TRIM4_TCA105_0_MASK GENMASK(19, 8)
> +#define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0)
> +#define TRIM5_TCA105_1_MASK GENMASK(23, 12)
> +#define TRIM5_TCA25_1_MASK GENMASK(11, 0)
> +
> #define VER1_TEMP_LOW_LIMIT 10000
> #define VER2_TEMP_LOW_LIMIT -40000
> #define VER2_TEMP_HIGH_LIMIT 125000
> @@ -128,6 +164,129 @@ static void imx8mm_tmu_probe_sel_all(struct
> imx8mm_tmu *tmu)
> writel_relaxed(val, tmu->base + TPS);
> }
>
> +static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev,
> + struct imx8mm_tmu *tmu)
> +{
> + struct device *dev = &pdev->dev;
> + u32 ana0;
> + int ret;
> +
> + ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0);
> + if (ret) {
> + dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n",
> ret);
> + return ret;
> + }
> +
> + writel(FIELD_PREP(TASR_BUF_VREF_MASK,
> + FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) |
> + FIELD_PREP(TASR_BUF_SLOPE_MASK,
> + FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)),
> + tmu->base + TASR);
> +
> + writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK,
> ana0)) |
> + FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0))
> |
> + ((ana0 & ANA0_EN) ? TCALIV_EN : 0),
> + tmu->base + TCALIV(0));
> +
> + return 0;
> +}
> +
> +static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev,
> + struct imx8mm_tmu *tmu)
> +{
> + struct device *dev = &pdev->dev;
> + struct nvmem_cell *cell;
> + u32 trim[4] = { 0 };
> + size_t len;
> + void *buf;
> +
> + cell = nvmem_cell_get(dev, "calib");
> + if (IS_ERR(cell))
> + return PTR_ERR(cell);
> +
> + buf = nvmem_cell_read(cell, &len);
> + nvmem_cell_put(cell);
> +
> + if (IS_ERR(buf))
> + return PTR_ERR(buf);
> +
> + memcpy(trim, buf, min(len, sizeof(trim)));
> + kfree(buf);
> +
> + if (len != 16) {
> + dev_err(dev,
> + "OCOTP nvmem cell length is %ld, must be 16.\n", len);
> + return -EINVAL;
> + }
> +
> + /* Blank sample hardware */
> + if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) {
> + /* Use a default 25C binary codes */
> + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
> + tmu->base + TCALIV(0));
> + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
> + tmu->base + TCALIV(1));
> + return 0;
> + }
> +
> + writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK,
> + FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) |
> + FIELD_PREP(TASR_BUF_SLOPE_MASK,
> + FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])),
> + tmu->base + TASR);
> +
> + writel(FIELD_PREP(TRIM_BJT_CUR_MASK,
> + FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) |
> + FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK,
> trim[0])) |
> + FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK,
> trim[0])) |
> + TRIM_EN_CH,
> + tmu->base + TRIM);
> +
> + writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
> + FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) |
> + (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) <<
> 4)) |
> + FIELD_PREP(TCALIV_SNSR105C_MASK,
> + FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])),
> + tmu->base + TCALIV(0));
> +
> + writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
> + FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) |
> + FIELD_PREP(TCALIV_SNSR105C_MASK,
> + FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])),
> + tmu->base + TCALIV(1));
> +
> + writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
> + FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) |
> + FIELD_PREP(TCALIV_SNSR105C_MASK,
> + FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])),
> + tmu->base + TCALIV(2));
> +
> + return 0;
> +}
> +
> +static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev,
> + struct imx8mm_tmu *tmu)
> +{
> + struct device *dev = &pdev->dev;
> +
> + /*
> + * Lack of calibration data OCOTP reference is not considered
> + * fatal to retain compatibility with old DTs. It is however
> + * strongly recommended to update such old DTs to get correct
> + * temperature compensation values for each SoC.
> + */
> + if (!of_find_property(pdev->dev.of_node, "nvmem-cells", NULL)) {
> + dev_warn(dev,
> + "No OCOTP nvmem reference found, SoC-specific
> calibration not loaded. Please update your DT.\n");
> + return 0;
> + }
> +
> + if (tmu->socdata->version == TMU_VER1)
> + return imx8mm_tmu_probe_set_calib_v1(pdev, tmu);
> +
> + return imx8mm_tmu_probe_set_calib_v2(pdev, tmu); }
> +
> static int imx8mm_tmu_probe(struct platform_device *pdev) {
> const struct thermal_soc_data *data;
> @@ -180,6 +339,10 @@ static int imx8mm_tmu_probe(struct platform_device
> *pdev)
>
> platform_set_drvdata(pdev, tmu);
>
> + ret = imx8mm_tmu_probe_set_calib(pdev, tmu);
> + if (ret)
> + goto disable_clk;
> +
> /* enable all the probes for V2 TMU */
> if (tmu->socdata->version == TMU_VER2)
> imx8mm_tmu_probe_sel_all(tmu);
> --
> 2.35.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
2022-11-26 22:47 ` [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Marek Vasut
2022-11-28 2:29 ` Peng Fan
@ 2022-11-28 8:34 ` Alexander Stein
2022-11-28 9:35 ` Marek Vasut
1 sibling, 1 reply; 12+ messages in thread
From: Alexander Stein @ 2022-11-28 8:34 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-pm, linux-arm-kernel, Adam Ford, Alice Guo, Amit Kucheria,
Daniel Lezcano, Fabio Estevam, Krzysztof Kozlowski, Li Jun,
Lucas Stach, Markus Niebel, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Rafael J . Wysocki, Richard Cochran,
Rob Herring, Sascha Hauer, Shawn Guo, Zhang Rui, devicetree,
Marek Vasut
Hi Marek,
Am Samstag, 26. November 2022, 23:47:39 CET schrieb Marek Vasut:
> The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
> calibration values in OCOTP. Add the OCOTP calibration values phandle so
> the TMU driver can perform this programming.
>
> The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Is there any source for the fuse addresses? I can only find
OCOTP_OCOTP_HW_OCOTP_ANA1 and a calibration description in TMU section in the
IMX8MNRM Rev 2, but I can't find any fuse for imx8mm and imx8mp.
Best regards,
Alexander
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Alice Guo <alice.guo@nxp.com>
> Cc: Amit Kucheria <amitk@kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Li Jun <jun.li@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Rafael J. Wysocki <rafael@kernel.org>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Zhang Rui <rui.zhang@intel.com>
> Cc: devicetree@vger.kernel.org
> To: linux-pm@vger.kernel.org
> To: linux-arm-kernel@lists.infradead.org
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
> 3 files changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index
> 513c2de0caa15..0cd7fff47c44d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -496,6 +496,8 @@ tmu: tmu@30260000 {
> compatible = "fsl,imx8mm-tmu";
> reg = <0x30260000 0x10000>;
> clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
> + nvmem-cells = <&tmu_calib>;
> + nvmem-cell-names = "calib";
> #thermal-sensor-cells = <0>;
> };
>
> @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
> reg = <0x10 4>;
> };
>
> + tmu_calib: calib@3c { /* 0x4f0 */
> + reg = <0x3c 4>;
> + };
> +
> fec_mac_address: mac-address@90 { /*
0x640 */
> reg = <0x90 6>;
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index
> 068f599cdf757..5eef9b274edde 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -498,6 +498,8 @@ tmu: tmu@30260000 {
> compatible = "fsl,imx8mn-tmu",
"fsl,imx8mm-tmu";
> reg = <0x30260000 0x10000>;
> clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
> + nvmem-cells = <&tmu_calib>;
> + nvmem-cell-names = "calib";
> #thermal-sensor-cells = <0>;
> };
>
> @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
> reg = <0x10 4>;
> };
>
> + tmu_calib: calib@3c { /* 0x4f0 */
> + reg = <0x3c 4>;
> + };
> +
> fec_mac_address: mac-address@90 { /*
0x640 */
> reg = <0x90 6>;
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> ddcd5e23ba47d..0173e394ad4d8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -380,6 +380,8 @@ tmu: tmu@30260000 {
> compatible = "fsl,imx8mp-tmu";
> reg = <0x30260000 0x10000>;
> clocks = <&clk
IMX8MP_CLK_TSENSOR_ROOT>;
> + nvmem-cells = <&tmu_calib>;
> + nvmem-cell-names = "calib";
> #thermal-sensor-cells = <1>;
> };
>
> @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */
> eth_mac2: mac-address@96 { /* 0x658 */
> reg = <0x96 6>;
> };
> +
> + tmu_calib: calib@264 { /* 0xd90-0xdc0
*/
> + reg = <0x264 0x10>;
> + };
> };
>
> anatop: clock-controller@30360000 {
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
2022-11-28 8:34 ` Alexander Stein
@ 2022-11-28 9:35 ` Marek Vasut
0 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2022-11-28 9:35 UTC (permalink / raw)
To: Alexander Stein
Cc: linux-pm, linux-arm-kernel, Adam Ford, Alice Guo, Amit Kucheria,
Daniel Lezcano, Fabio Estevam, Krzysztof Kozlowski, Li Jun,
Lucas Stach, Markus Niebel, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Rafael J . Wysocki, Richard Cochran,
Rob Herring, Sascha Hauer, Shawn Guo, Zhang Rui, devicetree
On 11/28/22 09:34, Alexander Stein wrote:
> Hi Marek,
Hi,
> Am Samstag, 26. November 2022, 23:47:39 CET schrieb Marek Vasut:
>> The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
>> calibration values in OCOTP. Add the OCOTP calibration values phandle so
>> the TMU driver can perform this programming.
>>
>> The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
>
> Is there any source for the fuse addresses? I can only find
> OCOTP_OCOTP_HW_OCOTP_ANA1 and a calibration description in TMU section in the
> IMX8MNRM Rev 2, but I can't find any fuse for imx8mm and imx8mp.
See 5/5 in this series, the offsets are pulled from U-Boot. The
documentation seems to be lacking in this case, I couldn't find anything
there either.
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-11-28 9:48 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-11-26 22:47 [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut
2022-11-26 22:47 ` [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Marek Vasut
2022-11-28 2:16 ` Peng Fan
2022-11-26 22:47 ` [PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation Marek Vasut
2022-11-28 2:18 ` Peng Fan
2022-11-26 22:47 ` [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Marek Vasut
2022-11-28 2:29 ` Peng Fan
2022-11-28 8:34 ` Alexander Stein
2022-11-28 9:35 ` Marek Vasut
2022-11-26 22:47 ` [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP Marek Vasut
2022-11-28 2:58 ` Peng Fan
2022-11-27 12:33 ` [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Krzysztof Kozlowski
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