* [PATCH v2 0/3] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors)
@ 2025-08-20 14:57 Denzeel Oliva
2025-08-20 14:57 ` [PATCH v2 1/3] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Denzeel Oliva @ 2025-08-20 14:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
Hi,
Two small fixes for Exynos990 CMU_TOP:
Correct PLL mux register selection (use PLL_CON0), add DPU_BUS and
CMUREF mux/div, and update clock IDs.
Fix mux/div bit widths and replace a few bogus divs with fixed-factor
clocks (HSI1/2 PCIe, USBDP debug); also fix OTP rate.
Changes in v2:
- In the first commit the divratio of
PLL_SHARED0_DIV3 should not be changed.
Please review.
Denzeel Oliva
---
Denzeel Oliva (3):
clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors
dt-bindings: clock: exynos990: Reorder IDs clocks and extend
clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF
drivers/clk/samsung/clk-exynos990.c | 154 +++++++++++++++----------
include/dt-bindings/clock/samsung,exynos990.h | 402 ++++++++++++++++++++++++++++++++--------------------------------
2 files changed, 297 insertions(+), 259 deletions(-)
---
base-commit: 886e5e7b0432360842303d587bb4a65d10741ae8
change-id: 20250819-2-ab6c8bdf07d7
Best regards,
--
Denzeel Oliva <wachiturroxd150@gmail.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/3] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors
2025-08-20 14:57 [PATCH v2 0/3] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
@ 2025-08-20 14:57 ` Denzeel Oliva
2025-08-20 14:57 ` [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend Denzeel Oliva
2025-08-20 14:57 ` [PATCH v2 3/3] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Denzeel Oliva
2 siblings, 0 replies; 7+ messages in thread
From: Denzeel Oliva @ 2025-08-20 14:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
Correct mux/div bit widths in CMU TOP (DPU, DSP_BUS, G2D_MSCL,
HSI0/1/2). Replace wrong divs with fixed-factor clocks for
HSI1/2 PCIe and USBDP debug. Also fix OTP rate. These align
with Exynos990 downstream cmucal and ensure correct parent/rate
selection.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
drivers/clk/samsung/clk-exynos990.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
index 8d3f193d2b4d4c2146d9b8b57d76605b88dc9bbb..a55991ebb77bcb2988071fc156dbe5c9b100215f 100644
--- a/drivers/clk/samsung/clk-exynos990.c
+++ b/drivers/clk/samsung/clk-exynos990.c
@@ -759,11 +759,11 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt",
mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2),
MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus",
- mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2),
+ mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 3),
MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d",
mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl",
- mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1),
+ mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm",
mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus",
@@ -775,7 +775,7 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
0, 2),
MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug",
mout_cmu_hsi0_usbdp_debug_p,
- CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2),
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 1),
MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus",
mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card",
@@ -788,7 +788,7 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
0, 2),
MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd",
mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
- 0, 1),
+ 0, 2),
MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus",
mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1),
MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie",
@@ -862,7 +862,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
- CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
+ CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2),
DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
@@ -889,7 +889,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug",
"gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
- 0, 3),
+ 0, 4),
DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
"gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
@@ -924,16 +924,11 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3),
DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
"gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4),
- DIV(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
- "gout_cmu_hsi0_usbdp_debug", CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
- 0, 4),
DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3),
DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card",
"gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
0, 9),
- DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
- CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7),
DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card",
"gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
0, 3),
@@ -942,8 +937,6 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
0, 3),
DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
- DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
- CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7),
DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
@@ -980,7 +973,17 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus",
CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu",
- CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4),
+ CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
+};
+
+static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
+ FFACTOR(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie",
+ "gout_cmu_hsi1_pcie", 1, 8, 0),
+ FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
+ FFACTOR(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
+ "gout_cmu_hsi0_usbdp_debug", 1, 8, 0),
+ FFACTOR(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie",
+ "gout_cmu_hsi2_pcie", 1, 8, 0),
};
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
@@ -1126,6 +1129,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
.div_clks = top_div_clks,
.nr_div_clks = ARRAY_SIZE(top_div_clks),
+ .fixed_factor_clks = cmu_top_ffactor,
+ .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.nr_clk_ids = CLKS_NR_TOP,
--
2.49.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend
2025-08-20 14:57 [PATCH v2 0/3] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
2025-08-20 14:57 ` [PATCH v2 1/3] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
@ 2025-08-20 14:57 ` Denzeel Oliva
2025-08-20 19:29 ` Conor Dooley
2025-08-20 14:57 ` [PATCH v2 3/3] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Denzeel Oliva
2 siblings, 1 reply; 7+ messages in thread
From: Denzeel Oliva @ 2025-08-20 14:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
Reorganize CMU_TOP clock definitions
and add missing clock definitions for DPU and CMUREF.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
include/dt-bindings/clock/samsung,exynos990.h | 402 ++++++++++++++++++++++++++++++++--------------------------------
1 file changed, 203 insertions(+), 199 deletions(-)
diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h
index 6b9df09d2822f1c8e5086a2fc0bda783ca224812..b384e271bf276a375f67659fc84e53350ea73c0e 100644
--- a/include/dt-bindings/clock/samsung,exynos990.h
+++ b/include/dt-bindings/clock/samsung,exynos990.h
@@ -9,205 +9,209 @@
#define _DT_BINDINGS_CLOCK_EXYNOS_990_H
/* CMU_TOP */
-#define CLK_FOUT_SHARED0_PLL 1
-#define CLK_FOUT_SHARED1_PLL 2
-#define CLK_FOUT_SHARED2_PLL 3
-#define CLK_FOUT_SHARED3_PLL 4
-#define CLK_FOUT_SHARED4_PLL 5
-#define CLK_FOUT_G3D_PLL 6
-#define CLK_FOUT_MMC_PLL 7
-#define CLK_MOUT_PLL_SHARED0 8
-#define CLK_MOUT_PLL_SHARED1 9
-#define CLK_MOUT_PLL_SHARED2 10
-#define CLK_MOUT_PLL_SHARED3 11
-#define CLK_MOUT_PLL_SHARED4 12
-#define CLK_MOUT_PLL_MMC 13
-#define CLK_MOUT_PLL_G3D 14
-#define CLK_MOUT_CMU_APM_BUS 15
-#define CLK_MOUT_CMU_AUD_CPU 16
-#define CLK_MOUT_CMU_BUS0_BUS 17
-#define CLK_MOUT_CMU_BUS1_BUS 18
-#define CLK_MOUT_CMU_BUS1_SSS 19
-#define CLK_MOUT_CMU_CIS_CLK0 20
-#define CLK_MOUT_CMU_CIS_CLK1 21
-#define CLK_MOUT_CMU_CIS_CLK2 22
-#define CLK_MOUT_CMU_CIS_CLK3 23
-#define CLK_MOUT_CMU_CIS_CLK4 24
-#define CLK_MOUT_CMU_CIS_CLK5 25
-#define CLK_MOUT_CMU_CMU_BOOST 26
-#define CLK_MOUT_CMU_CORE_BUS 27
-#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 28
-#define CLK_MOUT_CMU_CPUCL0_SWITCH 29
-#define CLK_MOUT_CMU_CPUCL1_SWITCH 30
-#define CLK_MOUT_CMU_CPUCL2_BUSP 31
-#define CLK_MOUT_CMU_CPUCL2_SWITCH 32
-#define CLK_MOUT_CMU_CSIS_BUS 33
-#define CLK_MOUT_CMU_CSIS_OIS_MCU 34
-#define CLK_MOUT_CMU_DNC_BUS 35
-#define CLK_MOUT_CMU_DNC_BUSM 36
-#define CLK_MOUT_CMU_DNS_BUS 37
-#define CLK_MOUT_CMU_DPU 38
-#define CLK_MOUT_CMU_DPU_ALT 39
-#define CLK_MOUT_CMU_DSP_BUS 40
-#define CLK_MOUT_CMU_G2D_G2D 41
-#define CLK_MOUT_CMU_G2D_MSCL 42
-#define CLK_MOUT_CMU_HPM 43
-#define CLK_MOUT_CMU_HSI0_BUS 44
-#define CLK_MOUT_CMU_HSI0_DPGTC 45
-#define CLK_MOUT_CMU_HSI0_USB31DRD 46
-#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 47
-#define CLK_MOUT_CMU_HSI1_BUS 48
-#define CLK_MOUT_CMU_HSI1_MMC_CARD 49
-#define CLK_MOUT_CMU_HSI1_PCIE 50
-#define CLK_MOUT_CMU_HSI1_UFS_CARD 51
-#define CLK_MOUT_CMU_HSI1_UFS_EMBD 52
-#define CLK_MOUT_CMU_HSI2_BUS 53
-#define CLK_MOUT_CMU_HSI2_PCIE 54
-#define CLK_MOUT_CMU_IPP_BUS 55
-#define CLK_MOUT_CMU_ITP_BUS 56
-#define CLK_MOUT_CMU_MCSC_BUS 57
-#define CLK_MOUT_CMU_MCSC_GDC 58
-#define CLK_MOUT_CMU_CMU_BOOST_CPU 59
-#define CLK_MOUT_CMU_MFC0_MFC0 60
-#define CLK_MOUT_CMU_MFC0_WFD 61
-#define CLK_MOUT_CMU_MIF_BUSP 62
-#define CLK_MOUT_CMU_MIF_SWITCH 63
-#define CLK_MOUT_CMU_NPU_BUS 64
-#define CLK_MOUT_CMU_PERIC0_BUS 65
-#define CLK_MOUT_CMU_PERIC0_IP 66
-#define CLK_MOUT_CMU_PERIC1_BUS 67
-#define CLK_MOUT_CMU_PERIC1_IP 68
-#define CLK_MOUT_CMU_PERIS_BUS 69
-#define CLK_MOUT_CMU_SSP_BUS 70
-#define CLK_MOUT_CMU_TNR_BUS 71
-#define CLK_MOUT_CMU_VRA_BUS 72
-#define CLK_DOUT_CMU_APM_BUS 73
-#define CLK_DOUT_CMU_AUD_CPU 74
-#define CLK_DOUT_CMU_BUS0_BUS 75
-#define CLK_DOUT_CMU_BUS1_BUS 76
-#define CLK_DOUT_CMU_BUS1_SSS 77
-#define CLK_DOUT_CMU_CIS_CLK0 78
-#define CLK_DOUT_CMU_CIS_CLK1 79
-#define CLK_DOUT_CMU_CIS_CLK2 80
-#define CLK_DOUT_CMU_CIS_CLK3 81
-#define CLK_DOUT_CMU_CIS_CLK4 82
-#define CLK_DOUT_CMU_CIS_CLK5 83
-#define CLK_DOUT_CMU_CMU_BOOST 84
-#define CLK_DOUT_CMU_CORE_BUS 85
-#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 86
-#define CLK_DOUT_CMU_CPUCL0_SWITCH 87
-#define CLK_DOUT_CMU_CPUCL1_SWITCH 88
-#define CLK_DOUT_CMU_CPUCL2_BUSP 89
-#define CLK_DOUT_CMU_CPUCL2_SWITCH 90
-#define CLK_DOUT_CMU_CSIS_BUS 91
-#define CLK_DOUT_CMU_CSIS_OIS_MCU 92
-#define CLK_DOUT_CMU_DNC_BUS 93
-#define CLK_DOUT_CMU_DNC_BUSM 94
-#define CLK_DOUT_CMU_DNS_BUS 95
-#define CLK_DOUT_CMU_DSP_BUS 96
-#define CLK_DOUT_CMU_G2D_G2D 97
-#define CLK_DOUT_CMU_G2D_MSCL 98
-#define CLK_DOUT_CMU_G3D_SWITCH 99
-#define CLK_DOUT_CMU_HPM 100
-#define CLK_DOUT_CMU_HSI0_BUS 101
-#define CLK_DOUT_CMU_HSI0_DPGTC 102
-#define CLK_DOUT_CMU_HSI0_USB31DRD 103
-#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 104
-#define CLK_DOUT_CMU_HSI1_BUS 105
-#define CLK_DOUT_CMU_HSI1_MMC_CARD 106
-#define CLK_DOUT_CMU_HSI1_PCIE 107
-#define CLK_DOUT_CMU_HSI1_UFS_CARD 108
-#define CLK_DOUT_CMU_HSI1_UFS_EMBD 109
-#define CLK_DOUT_CMU_HSI2_BUS 110
-#define CLK_DOUT_CMU_HSI2_PCIE 111
-#define CLK_DOUT_CMU_IPP_BUS 112
-#define CLK_DOUT_CMU_ITP_BUS 113
-#define CLK_DOUT_CMU_MCSC_BUS 114
-#define CLK_DOUT_CMU_MCSC_GDC 115
-#define CLK_DOUT_CMU_CMU_BOOST_CPU 116
-#define CLK_DOUT_CMU_MFC0_MFC0 117
-#define CLK_DOUT_CMU_MFC0_WFD 118
-#define CLK_DOUT_CMU_MIF_BUSP 119
-#define CLK_DOUT_CMU_NPU_BUS 120
-#define CLK_DOUT_CMU_OTP 121
-#define CLK_DOUT_CMU_PERIC0_BUS 122
-#define CLK_DOUT_CMU_PERIC0_IP 123
-#define CLK_DOUT_CMU_PERIC1_BUS 124
-#define CLK_DOUT_CMU_PERIC1_IP 125
-#define CLK_DOUT_CMU_PERIS_BUS 126
-#define CLK_DOUT_CMU_SSP_BUS 127
-#define CLK_DOUT_CMU_TNR_BUS 128
-#define CLK_DOUT_CMU_VRA_BUS 129
-#define CLK_DOUT_CMU_DPU 130
-#define CLK_DOUT_CMU_DPU_ALT 131
-#define CLK_DOUT_CMU_SHARED0_DIV2 132
-#define CLK_DOUT_CMU_SHARED0_DIV3 133
-#define CLK_DOUT_CMU_SHARED0_DIV4 134
-#define CLK_DOUT_CMU_SHARED1_DIV2 135
-#define CLK_DOUT_CMU_SHARED1_DIV3 136
-#define CLK_DOUT_CMU_SHARED1_DIV4 137
-#define CLK_DOUT_CMU_SHARED2_DIV2 138
-#define CLK_DOUT_CMU_SHARED4_DIV2 139
-#define CLK_DOUT_CMU_SHARED4_DIV3 140
-#define CLK_DOUT_CMU_SHARED4_DIV4 141
-#define CLK_GOUT_CMU_G3D_BUS 142
-#define CLK_GOUT_CMU_MIF_SWITCH 143
-#define CLK_GOUT_CMU_APM_BUS 144
-#define CLK_GOUT_CMU_AUD_CPU 145
-#define CLK_GOUT_CMU_BUS0_BUS 146
-#define CLK_GOUT_CMU_BUS1_BUS 147
-#define CLK_GOUT_CMU_BUS1_SSS 148
-#define CLK_GOUT_CMU_CIS_CLK0 149
-#define CLK_GOUT_CMU_CIS_CLK1 150
-#define CLK_GOUT_CMU_CIS_CLK2 151
-#define CLK_GOUT_CMU_CIS_CLK3 152
-#define CLK_GOUT_CMU_CIS_CLK4 153
-#define CLK_GOUT_CMU_CIS_CLK5 154
-#define CLK_GOUT_CMU_CORE_BUS 155
-#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 156
-#define CLK_GOUT_CMU_CPUCL0_SWITCH 157
-#define CLK_GOUT_CMU_CPUCL1_SWITCH 158
-#define CLK_GOUT_CMU_CPUCL2_BUSP 159
-#define CLK_GOUT_CMU_CPUCL2_SWITCH 160
-#define CLK_GOUT_CMU_CSIS_BUS 161
-#define CLK_GOUT_CMU_CSIS_OIS_MCU 162
-#define CLK_GOUT_CMU_DNC_BUS 163
-#define CLK_GOUT_CMU_DNC_BUSM 164
-#define CLK_GOUT_CMU_DNS_BUS 165
-#define CLK_GOUT_CMU_DPU 166
-#define CLK_GOUT_CMU_DPU_BUS 167
-#define CLK_GOUT_CMU_DSP_BUS 168
-#define CLK_GOUT_CMU_G2D_G2D 169
-#define CLK_GOUT_CMU_G2D_MSCL 170
-#define CLK_GOUT_CMU_G3D_SWITCH 171
-#define CLK_GOUT_CMU_HPM 172
-#define CLK_GOUT_CMU_HSI0_BUS 173
-#define CLK_GOUT_CMU_HSI0_DPGTC 174
-#define CLK_GOUT_CMU_HSI0_USB31DRD 175
-#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 176
-#define CLK_GOUT_CMU_HSI1_BUS 177
-#define CLK_GOUT_CMU_HSI1_MMC_CARD 178
-#define CLK_GOUT_CMU_HSI1_PCIE 179
-#define CLK_GOUT_CMU_HSI1_UFS_CARD 180
-#define CLK_GOUT_CMU_HSI1_UFS_EMBD 181
-#define CLK_GOUT_CMU_HSI2_BUS 182
-#define CLK_GOUT_CMU_HSI2_PCIE 183
-#define CLK_GOUT_CMU_IPP_BUS 184
-#define CLK_GOUT_CMU_ITP_BUS 185
-#define CLK_GOUT_CMU_MCSC_BUS 186
-#define CLK_GOUT_CMU_MCSC_GDC 187
-#define CLK_GOUT_CMU_MFC0_MFC0 188
-#define CLK_GOUT_CMU_MFC0_WFD 189
-#define CLK_GOUT_CMU_MIF_BUSP 190
-#define CLK_GOUT_CMU_NPU_BUS 191
-#define CLK_GOUT_CMU_PERIC0_BUS 192
-#define CLK_GOUT_CMU_PERIC0_IP 193
-#define CLK_GOUT_CMU_PERIC1_BUS 194
-#define CLK_GOUT_CMU_PERIC1_IP 195
-#define CLK_GOUT_CMU_PERIS_BUS 196
-#define CLK_GOUT_CMU_SSP_BUS 197
-#define CLK_GOUT_CMU_TNR_BUS 198
-#define CLK_GOUT_CMU_VRA_BUS 199
+#define CLK_FOUT_G3D_PLL 1
+#define CLK_FOUT_MMC_PLL 2
+#define CLK_FOUT_SHARED0_PLL 3
+#define CLK_FOUT_SHARED1_PLL 4
+#define CLK_FOUT_SHARED2_PLL 5
+#define CLK_FOUT_SHARED3_PLL 6
+#define CLK_FOUT_SHARED4_PLL 7
+#define CLK_MOUT_PLL_G3D 8
+#define CLK_MOUT_PLL_MMC 9
+#define CLK_MOUT_PLL_SHARED0 10
+#define CLK_MOUT_PLL_SHARED1 11
+#define CLK_MOUT_PLL_SHARED2 12
+#define CLK_MOUT_PLL_SHARED3 13
+#define CLK_MOUT_PLL_SHARED4 14
+#define CLK_MOUT_CMU_DPU_BUS 15
+#define CLK_MOUT_CMU_APM_BUS 16
+#define CLK_MOUT_CMU_AUD_CPU 17
+#define CLK_MOUT_CMU_BUS0_BUS 18
+#define CLK_MOUT_CMU_BUS1_BUS 19
+#define CLK_MOUT_CMU_BUS1_SSS 20
+#define CLK_MOUT_CMU_CIS_CLK0 21
+#define CLK_MOUT_CMU_CIS_CLK1 22
+#define CLK_MOUT_CMU_CIS_CLK2 23
+#define CLK_MOUT_CMU_CIS_CLK3 24
+#define CLK_MOUT_CMU_CIS_CLK4 25
+#define CLK_MOUT_CMU_CIS_CLK5 26
+#define CLK_MOUT_CMU_CMU_BOOST 27
+#define CLK_MOUT_CMU_CORE_BUS 28
+#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 29
+#define CLK_MOUT_CMU_CPUCL0_SWITCH 30
+#define CLK_MOUT_CMU_CPUCL1_SWITCH 31
+#define CLK_MOUT_CMU_CPUCL2_BUSP 32
+#define CLK_MOUT_CMU_CPUCL2_SWITCH 33
+#define CLK_MOUT_CMU_CSIS_BUS 34
+#define CLK_MOUT_CMU_CSIS_OIS_MCU 35
+#define CLK_MOUT_CMU_DNC_BUS 36
+#define CLK_MOUT_CMU_DNC_BUSM 37
+#define CLK_MOUT_CMU_DNS_BUS 38
+#define CLK_MOUT_CMU_DPU 39
+#define CLK_MOUT_CMU_DPU_ALT 40
+#define CLK_MOUT_CMU_DSP_BUS 41
+#define CLK_MOUT_CMU_G2D_G2D 42
+#define CLK_MOUT_CMU_G2D_MSCL 43
+#define CLK_MOUT_CMU_HPM 44
+#define CLK_MOUT_CMU_HSI0_BUS 45
+#define CLK_MOUT_CMU_HSI0_DPGTC 46
+#define CLK_MOUT_CMU_HSI0_USB31DRD 47
+#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 48
+#define CLK_MOUT_CMU_HSI1_BUS 49
+#define CLK_MOUT_CMU_HSI1_MMC_CARD 50
+#define CLK_MOUT_CMU_HSI1_PCIE 51
+#define CLK_MOUT_CMU_HSI1_UFS_CARD 52
+#define CLK_MOUT_CMU_HSI1_UFS_EMBD 53
+#define CLK_MOUT_CMU_HSI2_BUS 54
+#define CLK_MOUT_CMU_HSI2_PCIE 55
+#define CLK_MOUT_CMU_IPP_BUS 56
+#define CLK_MOUT_CMU_ITP_BUS 57
+#define CLK_MOUT_CMU_MCSC_BUS 58
+#define CLK_MOUT_CMU_MCSC_GDC 59
+#define CLK_MOUT_CMU_CMU_BOOST_CPU 60
+#define CLK_MOUT_CMU_MFC0_MFC0 61
+#define CLK_MOUT_CMU_MFC0_WFD 62
+#define CLK_MOUT_CMU_MIF_BUSP 63
+#define CLK_MOUT_CMU_MIF_SWITCH 64
+#define CLK_MOUT_CMU_NPU_BUS 65
+#define CLK_MOUT_CMU_PERIC0_BUS 66
+#define CLK_MOUT_CMU_PERIC0_IP 67
+#define CLK_MOUT_CMU_PERIC1_BUS 68
+#define CLK_MOUT_CMU_PERIC1_IP 69
+#define CLK_MOUT_CMU_PERIS_BUS 70
+#define CLK_MOUT_CMU_SSP_BUS 71
+#define CLK_MOUT_CMU_TNR_BUS 72
+#define CLK_MOUT_CMU_VRA_BUS 73
+#define CLK_MOUT_CMU_CMUREF 74
+#define CLK_MOUT_CMU_CLK_CMUREF 75
+#define CLK_DOUT_CMU_APM_BUS 76
+#define CLK_DOUT_CMU_AUD_CPU 77
+#define CLK_DOUT_CMU_BUS0_BUS 78
+#define CLK_DOUT_CMU_BUS1_BUS 79
+#define CLK_DOUT_CMU_BUS1_SSS 80
+#define CLK_DOUT_CMU_CIS_CLK0 81
+#define CLK_DOUT_CMU_CIS_CLK1 82
+#define CLK_DOUT_CMU_CIS_CLK2 83
+#define CLK_DOUT_CMU_CIS_CLK3 84
+#define CLK_DOUT_CMU_CIS_CLK4 85
+#define CLK_DOUT_CMU_CIS_CLK5 86
+#define CLK_DOUT_CMU_CMU_BOOST 87
+#define CLK_DOUT_CMU_CORE_BUS 88
+#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 89
+#define CLK_DOUT_CMU_CPUCL0_SWITCH 90
+#define CLK_DOUT_CMU_CPUCL1_SWITCH 91
+#define CLK_DOUT_CMU_CPUCL2_BUSP 92
+#define CLK_DOUT_CMU_CPUCL2_SWITCH 93
+#define CLK_DOUT_CMU_CSIS_BUS 94
+#define CLK_DOUT_CMU_CSIS_OIS_MCU 95
+#define CLK_DOUT_CMU_DNC_BUS 96
+#define CLK_DOUT_CMU_DNC_BUSM 97
+#define CLK_DOUT_CMU_DNS_BUS 98
+#define CLK_DOUT_CMU_DSP_BUS 99
+#define CLK_DOUT_CMU_G2D_G2D 100
+#define CLK_DOUT_CMU_G2D_MSCL 101
+#define CLK_DOUT_CMU_G3D_SWITCH 102
+#define CLK_DOUT_CMU_HPM 103
+#define CLK_DOUT_CMU_HSI0_BUS 104
+#define CLK_DOUT_CMU_HSI0_DPGTC 105
+#define CLK_DOUT_CMU_HSI0_USB31DRD 106
+#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 107
+#define CLK_DOUT_CMU_HSI1_BUS 108
+#define CLK_DOUT_CMU_HSI1_MMC_CARD 109
+#define CLK_DOUT_CMU_HSI1_PCIE 110
+#define CLK_DOUT_CMU_HSI1_UFS_CARD 111
+#define CLK_DOUT_CMU_HSI1_UFS_EMBD 112
+#define CLK_DOUT_CMU_HSI2_BUS 113
+#define CLK_DOUT_CMU_HSI2_PCIE 114
+#define CLK_DOUT_CMU_IPP_BUS 115
+#define CLK_DOUT_CMU_ITP_BUS 116
+#define CLK_DOUT_CMU_MCSC_BUS 117
+#define CLK_DOUT_CMU_MCSC_GDC 118
+#define CLK_DOUT_CMU_CMU_BOOST_CPU 119
+#define CLK_DOUT_CMU_MFC0_MFC0 120
+#define CLK_DOUT_CMU_MFC0_WFD 121
+#define CLK_DOUT_CMU_MIF_BUSP 122
+#define CLK_DOUT_CMU_NPU_BUS 123
+#define CLK_DOUT_CMU_OTP 124
+#define CLK_DOUT_CMU_PERIC0_BUS 125
+#define CLK_DOUT_CMU_PERIC0_IP 126
+#define CLK_DOUT_CMU_PERIC1_BUS 127
+#define CLK_DOUT_CMU_PERIC1_IP 128
+#define CLK_DOUT_CMU_PERIS_BUS 129
+#define CLK_DOUT_CMU_SSP_BUS 130
+#define CLK_DOUT_CMU_TNR_BUS 131
+#define CLK_DOUT_CMU_VRA_BUS 132
+#define CLK_DOUT_CMU_DPU 133
+#define CLK_DOUT_CMU_DPU_ALT 134
+#define CLK_DOUT_CMU_CLK_CMUREF 135
+#define CLK_DOUT_CMU_SHARED0_DIV2 136
+#define CLK_DOUT_CMU_SHARED0_DIV3 137
+#define CLK_DOUT_CMU_SHARED0_DIV4 138
+#define CLK_DOUT_CMU_SHARED1_DIV2 139
+#define CLK_DOUT_CMU_SHARED1_DIV3 140
+#define CLK_DOUT_CMU_SHARED1_DIV4 141
+#define CLK_DOUT_CMU_SHARED2_DIV2 142
+#define CLK_DOUT_CMU_SHARED4_DIV2 145
+#define CLK_DOUT_CMU_SHARED4_DIV3 146
+#define CLK_DOUT_CMU_SHARED4_DIV4 147
+#define CLK_GOUT_CMU_G3D_BUS 148
+#define CLK_GOUT_CMU_MIF_SWITCH 149
+#define CLK_GOUT_CMU_APM_BUS 150
+#define CLK_GOUT_CMU_AUD_CPU 151
+#define CLK_GOUT_CMU_BUS0_BUS 152
+#define CLK_GOUT_CMU_BUS1_BUS 153
+#define CLK_GOUT_CMU_BUS1_SSS 154
+#define CLK_GOUT_CMU_CIS_CLK0 155
+#define CLK_GOUT_CMU_CIS_CLK1 156
+#define CLK_GOUT_CMU_CIS_CLK2 157
+#define CLK_GOUT_CMU_CIS_CLK3 158
+#define CLK_GOUT_CMU_CIS_CLK4 159
+#define CLK_GOUT_CMU_CIS_CLK5 160
+#define CLK_GOUT_CMU_CORE_BUS 161
+#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 162
+#define CLK_GOUT_CMU_CPUCL0_SWITCH 163
+#define CLK_GOUT_CMU_CPUCL1_SWITCH 164
+#define CLK_GOUT_CMU_CPUCL2_BUSP 165
+#define CLK_GOUT_CMU_CPUCL2_SWITCH 166
+#define CLK_GOUT_CMU_CSIS_BUS 167
+#define CLK_GOUT_CMU_CSIS_OIS_MCU 168
+#define CLK_GOUT_CMU_DNC_BUS 169
+#define CLK_GOUT_CMU_DNC_BUSM 170
+#define CLK_GOUT_CMU_DNS_BUS 171
+#define CLK_GOUT_CMU_DPU 172
+#define CLK_GOUT_CMU_DPU_BUS 173
+#define CLK_GOUT_CMU_DSP_BUS 174
+#define CLK_GOUT_CMU_G2D_G2D 175
+#define CLK_GOUT_CMU_G2D_MSCL 176
+#define CLK_GOUT_CMU_G3D_SWITCH 177
+#define CLK_GOUT_CMU_HPM 178
+#define CLK_GOUT_CMU_HSI0_BUS 179
+#define CLK_GOUT_CMU_HSI0_DPGTC 180
+#define CLK_GOUT_CMU_HSI0_USB31DRD 181
+#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 182
+#define CLK_GOUT_CMU_HSI1_BUS 183
+#define CLK_GOUT_CMU_HSI1_MMC_CARD 184
+#define CLK_GOUT_CMU_HSI1_PCIE 185
+#define CLK_GOUT_CMU_HSI1_UFS_CARD 186
+#define CLK_GOUT_CMU_HSI1_UFS_EMBD 187
+#define CLK_GOUT_CMU_HSI2_BUS 188
+#define CLK_GOUT_CMU_HSI2_PCIE 189
+#define CLK_GOUT_CMU_IPP_BUS 190
+#define CLK_GOUT_CMU_ITP_BUS 191
+#define CLK_GOUT_CMU_MCSC_BUS 192
+#define CLK_GOUT_CMU_MCSC_GDC 193
+#define CLK_GOUT_CMU_MFC0_MFC0 194
+#define CLK_GOUT_CMU_MFC0_WFD 195
+#define CLK_GOUT_CMU_MIF_BUSP 196
+#define CLK_GOUT_CMU_NPU_BUS 197
+#define CLK_GOUT_CMU_PERIC0_BUS 198
+#define CLK_GOUT_CMU_PERIC0_IP 199
+#define CLK_GOUT_CMU_PERIC1_BUS 200
+#define CLK_GOUT_CMU_PERIC1_IP 201
+#define CLK_GOUT_CMU_PERIS_BUS 202
+#define CLK_GOUT_CMU_SSP_BUS 203
+#define CLK_GOUT_CMU_TNR_BUS 204
+#define CLK_GOUT_CMU_VRA_BUS 205
/* CMU_HSI0 */
#define CLK_MOUT_HSI0_BUS_USER 1
--
2.49.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF
2025-08-20 14:57 [PATCH v2 0/3] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
2025-08-20 14:57 ` [PATCH v2 1/3] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
2025-08-20 14:57 ` [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend Denzeel Oliva
@ 2025-08-20 14:57 ` Denzeel Oliva
2 siblings, 0 replies; 7+ messages in thread
From: Denzeel Oliva @ 2025-08-20 14:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
Switch PLL muxes to PLL_CON0 to correct parent selection and
clock rates. Add DPU_BUS and CMUREF mux/div and their register
hooks and parents.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
drivers/clk/samsung/clk-exynos990.c | 121 ++++++++++++++++++++++++++++++++++++++++++++++----------------------------
1 file changed, 75 insertions(+), 46 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
index a55991ebb77bcb2988071fc156dbe5c9b100215f..c5f1dbaf45b6a718994c1dfa9f204cfccd74cb16 100644
--- a/drivers/clk/samsung/clk-exynos990.c
+++ b/drivers/clk/samsung/clk-exynos990.c
@@ -45,6 +45,7 @@
#define PLL_CON3_PLL_SHARED3 0x024c
#define PLL_CON0_PLL_SHARED4 0x0280
#define PLL_CON3_PLL_SHARED4 0x028c
+#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
@@ -103,6 +104,8 @@
#define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
#define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
+#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0
+#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
#define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
@@ -162,6 +165,7 @@
#define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
#define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
#define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
+#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0
#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
@@ -239,13 +243,21 @@ static const unsigned long top_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_SHARED2,
PLL_LOCKTIME_PLL_SHARED3,
PLL_LOCKTIME_PLL_SHARED4,
+ PLL_CON0_PLL_G3D,
PLL_CON3_PLL_G3D,
+ PLL_CON0_PLL_MMC,
PLL_CON3_PLL_MMC,
+ PLL_CON0_PLL_SHARED0,
PLL_CON3_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED1,
PLL_CON3_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED2,
PLL_CON3_PLL_SHARED2,
+ PLL_CON0_PLL_SHARED3,
PLL_CON3_PLL_SHARED3,
+ PLL_CON0_PLL_SHARED4,
PLL_CON3_PLL_SHARED4,
+ CLK_CON_MUX_CLKCMU_DPU_BUS,
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
@@ -304,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
+ CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
+ CLK_CON_MUX_MUX_CMU_CMUREF,
CLK_CON_DIV_CLKCMU_APM_BUS,
CLK_CON_DIV_CLKCMU_AUD_CPU,
CLK_CON_DIV_CLKCMU_BUS0_BUS,
@@ -363,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_VRA_BUS,
CLK_CON_DIV_DIV_CLKCMU_DPU,
CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
+ CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
CLK_CON_DIV_PLL_SHARED0_DIV2,
CLK_CON_DIV_PLL_SHARED0_DIV3,
CLK_CON_DIV_PLL_SHARED0_DIV4,
@@ -434,6 +449,10 @@ static const unsigned long top_clk_regs[] __initconst = {
};
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
+ PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
+ PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
+ PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
+ PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
PLL(pll_0717x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
PLL(pll_0717x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
@@ -444,20 +463,18 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
PLL(pll_0717x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
- PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
- PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
- PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
- PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
};
/* Parent clock list for CMU_TOP muxes */
+PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
+PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
-PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
-PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
+PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu",
+ "dout_cmu_dpu_alt" };
PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
"dout_cmu_shared2_div2" };
PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
@@ -507,7 +524,7 @@ PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared4_pll",
"dout_cmu_shared0_div2",
"fout_shared2_pll",
"dout_cmu_shared0_div4" };
-PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
+PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
"dout_cmu_shared0_div2",
"fout_shared2_pll",
"dout_cmu_shared0_div4" };
@@ -577,7 +594,7 @@ PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div3",
"dout_cmu_shared4_div3",
"dout_cmu_shared2_div2",
"fout_mmc_pll", "oscclk", "oscclk" };
-PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
+PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
"fout_mmc_pll",
"dout_cmu_shared0_div4" };
PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" };
@@ -672,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
"dout_cmu_shared4_div2",
"dout_cmu_shared0_div4",
"dout_cmu_shared4_div3" };
+PNAME(mout_cmu_cmuref_p) = { "oscclk",
+ "dout_cmu_clk_cmuref" };
+PNAME(mout_cmu_clk_cmuref_p) = { "dout_cmu_shared0_div4",
+ "dout_cmu_shared1_div4",
+ "dout_cmu_shared2_div2",
+ "oscclk" };
/*
* Register name to clock name mangling strategy used in this file
@@ -688,20 +711,22 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
*/
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
+ PLL_CON0_PLL_MMC, 4, 1),
+ MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
+ PLL_CON0_PLL_G3D, 4, 1),
MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
- PLL_CON3_PLL_SHARED0, 4, 1),
+ PLL_CON0_PLL_SHARED0, 4, 1),
MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
- PLL_CON3_PLL_SHARED1, 4, 1),
+ PLL_CON0_PLL_SHARED1, 4, 1),
MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
- PLL_CON3_PLL_SHARED2, 4, 1),
+ PLL_CON0_PLL_SHARED2, 4, 1),
MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
- PLL_CON3_PLL_SHARED3, 4, 1),
+ PLL_CON0_PLL_SHARED3, 4, 1),
MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
PLL_CON0_PLL_SHARED4, 4, 1),
- MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
- PLL_CON0_PLL_MMC, 4, 1),
- MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
- PLL_CON0_PLL_G3D, 4, 1),
+ MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus",
+ mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1),
MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
@@ -830,37 +855,13 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
+ MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref",
+ mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
+ MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref",
+ mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2),
};
static const struct samsung_div_clock top_div_clks[] __initconst = {
- /* SHARED0 region*/
- DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
- CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
- DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
- CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
- DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
- CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
-
- /* SHARED1 region*/
- DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
- CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
- DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
- CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
- DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
- CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
-
- /* SHARED2 region */
- DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
- CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
-
- /* SHARED4 region*/
- DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
- CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
- DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
- CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
- DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4",
- CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
-
DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2),
DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
@@ -887,7 +888,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2),
DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
- DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug",
+ DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_dbg_bus",
"gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
0, 4),
DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
@@ -972,8 +973,36 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus",
CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
- DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu",
+ DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu",
CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
+ DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus",
+ CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4),
+ DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref",
+ CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
+ /* SHARED0 region*/
+ DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
+ CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+ DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
+ CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+ DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
+ CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+ /* SHARED1 region*/
+ DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
+ CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+ DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
+ CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+ DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
+ CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+ /* SHARED2 region */
+ DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
+ CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
+ /* SHARED4 region*/
+ DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
+ CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
+ DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
+ CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
+ DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "dout_cmu_shared4_div2",
+ CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
};
static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
--
2.49.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend
2025-08-20 14:57 ` [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend Denzeel Oliva
@ 2025-08-20 19:29 ` Conor Dooley
2025-08-23 17:27 ` Denzeel Oliva
0 siblings, 1 reply; 7+ messages in thread
From: Conor Dooley @ 2025-08-20 19:29 UTC (permalink / raw)
To: Denzeel Oliva
Cc: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, linux-samsung-soc, linux-clk, linux-arm-kernel,
linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 16705 bytes --]
On Wed, Aug 20, 2025 at 09:57:23AM -0500, Denzeel Oliva wrote:
> Reorganize CMU_TOP clock definitions
> and add missing clock definitions for DPU and CMUREF.
>
> Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
This looks like a massive ABI break, where is the justification for
doing it?
Cheers,
Conor.
> ---
> include/dt-bindings/clock/samsung,exynos990.h | 402 ++++++++++++++++++++++++++++++++--------------------------------
> 1 file changed, 203 insertions(+), 199 deletions(-)
>
> diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h
> index 6b9df09d2822f1c8e5086a2fc0bda783ca224812..b384e271bf276a375f67659fc84e53350ea73c0e 100644
> --- a/include/dt-bindings/clock/samsung,exynos990.h
> +++ b/include/dt-bindings/clock/samsung,exynos990.h
> @@ -9,205 +9,209 @@
> #define _DT_BINDINGS_CLOCK_EXYNOS_990_H
>
> /* CMU_TOP */
> -#define CLK_FOUT_SHARED0_PLL 1
> -#define CLK_FOUT_SHARED1_PLL 2
> -#define CLK_FOUT_SHARED2_PLL 3
> -#define CLK_FOUT_SHARED3_PLL 4
> -#define CLK_FOUT_SHARED4_PLL 5
> -#define CLK_FOUT_G3D_PLL 6
> -#define CLK_FOUT_MMC_PLL 7
> -#define CLK_MOUT_PLL_SHARED0 8
> -#define CLK_MOUT_PLL_SHARED1 9
> -#define CLK_MOUT_PLL_SHARED2 10
> -#define CLK_MOUT_PLL_SHARED3 11
> -#define CLK_MOUT_PLL_SHARED4 12
> -#define CLK_MOUT_PLL_MMC 13
> -#define CLK_MOUT_PLL_G3D 14
> -#define CLK_MOUT_CMU_APM_BUS 15
> -#define CLK_MOUT_CMU_AUD_CPU 16
> -#define CLK_MOUT_CMU_BUS0_BUS 17
> -#define CLK_MOUT_CMU_BUS1_BUS 18
> -#define CLK_MOUT_CMU_BUS1_SSS 19
> -#define CLK_MOUT_CMU_CIS_CLK0 20
> -#define CLK_MOUT_CMU_CIS_CLK1 21
> -#define CLK_MOUT_CMU_CIS_CLK2 22
> -#define CLK_MOUT_CMU_CIS_CLK3 23
> -#define CLK_MOUT_CMU_CIS_CLK4 24
> -#define CLK_MOUT_CMU_CIS_CLK5 25
> -#define CLK_MOUT_CMU_CMU_BOOST 26
> -#define CLK_MOUT_CMU_CORE_BUS 27
> -#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 28
> -#define CLK_MOUT_CMU_CPUCL0_SWITCH 29
> -#define CLK_MOUT_CMU_CPUCL1_SWITCH 30
> -#define CLK_MOUT_CMU_CPUCL2_BUSP 31
> -#define CLK_MOUT_CMU_CPUCL2_SWITCH 32
> -#define CLK_MOUT_CMU_CSIS_BUS 33
> -#define CLK_MOUT_CMU_CSIS_OIS_MCU 34
> -#define CLK_MOUT_CMU_DNC_BUS 35
> -#define CLK_MOUT_CMU_DNC_BUSM 36
> -#define CLK_MOUT_CMU_DNS_BUS 37
> -#define CLK_MOUT_CMU_DPU 38
> -#define CLK_MOUT_CMU_DPU_ALT 39
> -#define CLK_MOUT_CMU_DSP_BUS 40
> -#define CLK_MOUT_CMU_G2D_G2D 41
> -#define CLK_MOUT_CMU_G2D_MSCL 42
> -#define CLK_MOUT_CMU_HPM 43
> -#define CLK_MOUT_CMU_HSI0_BUS 44
> -#define CLK_MOUT_CMU_HSI0_DPGTC 45
> -#define CLK_MOUT_CMU_HSI0_USB31DRD 46
> -#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 47
> -#define CLK_MOUT_CMU_HSI1_BUS 48
> -#define CLK_MOUT_CMU_HSI1_MMC_CARD 49
> -#define CLK_MOUT_CMU_HSI1_PCIE 50
> -#define CLK_MOUT_CMU_HSI1_UFS_CARD 51
> -#define CLK_MOUT_CMU_HSI1_UFS_EMBD 52
> -#define CLK_MOUT_CMU_HSI2_BUS 53
> -#define CLK_MOUT_CMU_HSI2_PCIE 54
> -#define CLK_MOUT_CMU_IPP_BUS 55
> -#define CLK_MOUT_CMU_ITP_BUS 56
> -#define CLK_MOUT_CMU_MCSC_BUS 57
> -#define CLK_MOUT_CMU_MCSC_GDC 58
> -#define CLK_MOUT_CMU_CMU_BOOST_CPU 59
> -#define CLK_MOUT_CMU_MFC0_MFC0 60
> -#define CLK_MOUT_CMU_MFC0_WFD 61
> -#define CLK_MOUT_CMU_MIF_BUSP 62
> -#define CLK_MOUT_CMU_MIF_SWITCH 63
> -#define CLK_MOUT_CMU_NPU_BUS 64
> -#define CLK_MOUT_CMU_PERIC0_BUS 65
> -#define CLK_MOUT_CMU_PERIC0_IP 66
> -#define CLK_MOUT_CMU_PERIC1_BUS 67
> -#define CLK_MOUT_CMU_PERIC1_IP 68
> -#define CLK_MOUT_CMU_PERIS_BUS 69
> -#define CLK_MOUT_CMU_SSP_BUS 70
> -#define CLK_MOUT_CMU_TNR_BUS 71
> -#define CLK_MOUT_CMU_VRA_BUS 72
> -#define CLK_DOUT_CMU_APM_BUS 73
> -#define CLK_DOUT_CMU_AUD_CPU 74
> -#define CLK_DOUT_CMU_BUS0_BUS 75
> -#define CLK_DOUT_CMU_BUS1_BUS 76
> -#define CLK_DOUT_CMU_BUS1_SSS 77
> -#define CLK_DOUT_CMU_CIS_CLK0 78
> -#define CLK_DOUT_CMU_CIS_CLK1 79
> -#define CLK_DOUT_CMU_CIS_CLK2 80
> -#define CLK_DOUT_CMU_CIS_CLK3 81
> -#define CLK_DOUT_CMU_CIS_CLK4 82
> -#define CLK_DOUT_CMU_CIS_CLK5 83
> -#define CLK_DOUT_CMU_CMU_BOOST 84
> -#define CLK_DOUT_CMU_CORE_BUS 85
> -#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 86
> -#define CLK_DOUT_CMU_CPUCL0_SWITCH 87
> -#define CLK_DOUT_CMU_CPUCL1_SWITCH 88
> -#define CLK_DOUT_CMU_CPUCL2_BUSP 89
> -#define CLK_DOUT_CMU_CPUCL2_SWITCH 90
> -#define CLK_DOUT_CMU_CSIS_BUS 91
> -#define CLK_DOUT_CMU_CSIS_OIS_MCU 92
> -#define CLK_DOUT_CMU_DNC_BUS 93
> -#define CLK_DOUT_CMU_DNC_BUSM 94
> -#define CLK_DOUT_CMU_DNS_BUS 95
> -#define CLK_DOUT_CMU_DSP_BUS 96
> -#define CLK_DOUT_CMU_G2D_G2D 97
> -#define CLK_DOUT_CMU_G2D_MSCL 98
> -#define CLK_DOUT_CMU_G3D_SWITCH 99
> -#define CLK_DOUT_CMU_HPM 100
> -#define CLK_DOUT_CMU_HSI0_BUS 101
> -#define CLK_DOUT_CMU_HSI0_DPGTC 102
> -#define CLK_DOUT_CMU_HSI0_USB31DRD 103
> -#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 104
> -#define CLK_DOUT_CMU_HSI1_BUS 105
> -#define CLK_DOUT_CMU_HSI1_MMC_CARD 106
> -#define CLK_DOUT_CMU_HSI1_PCIE 107
> -#define CLK_DOUT_CMU_HSI1_UFS_CARD 108
> -#define CLK_DOUT_CMU_HSI1_UFS_EMBD 109
> -#define CLK_DOUT_CMU_HSI2_BUS 110
> -#define CLK_DOUT_CMU_HSI2_PCIE 111
> -#define CLK_DOUT_CMU_IPP_BUS 112
> -#define CLK_DOUT_CMU_ITP_BUS 113
> -#define CLK_DOUT_CMU_MCSC_BUS 114
> -#define CLK_DOUT_CMU_MCSC_GDC 115
> -#define CLK_DOUT_CMU_CMU_BOOST_CPU 116
> -#define CLK_DOUT_CMU_MFC0_MFC0 117
> -#define CLK_DOUT_CMU_MFC0_WFD 118
> -#define CLK_DOUT_CMU_MIF_BUSP 119
> -#define CLK_DOUT_CMU_NPU_BUS 120
> -#define CLK_DOUT_CMU_OTP 121
> -#define CLK_DOUT_CMU_PERIC0_BUS 122
> -#define CLK_DOUT_CMU_PERIC0_IP 123
> -#define CLK_DOUT_CMU_PERIC1_BUS 124
> -#define CLK_DOUT_CMU_PERIC1_IP 125
> -#define CLK_DOUT_CMU_PERIS_BUS 126
> -#define CLK_DOUT_CMU_SSP_BUS 127
> -#define CLK_DOUT_CMU_TNR_BUS 128
> -#define CLK_DOUT_CMU_VRA_BUS 129
> -#define CLK_DOUT_CMU_DPU 130
> -#define CLK_DOUT_CMU_DPU_ALT 131
> -#define CLK_DOUT_CMU_SHARED0_DIV2 132
> -#define CLK_DOUT_CMU_SHARED0_DIV3 133
> -#define CLK_DOUT_CMU_SHARED0_DIV4 134
> -#define CLK_DOUT_CMU_SHARED1_DIV2 135
> -#define CLK_DOUT_CMU_SHARED1_DIV3 136
> -#define CLK_DOUT_CMU_SHARED1_DIV4 137
> -#define CLK_DOUT_CMU_SHARED2_DIV2 138
> -#define CLK_DOUT_CMU_SHARED4_DIV2 139
> -#define CLK_DOUT_CMU_SHARED4_DIV3 140
> -#define CLK_DOUT_CMU_SHARED4_DIV4 141
> -#define CLK_GOUT_CMU_G3D_BUS 142
> -#define CLK_GOUT_CMU_MIF_SWITCH 143
> -#define CLK_GOUT_CMU_APM_BUS 144
> -#define CLK_GOUT_CMU_AUD_CPU 145
> -#define CLK_GOUT_CMU_BUS0_BUS 146
> -#define CLK_GOUT_CMU_BUS1_BUS 147
> -#define CLK_GOUT_CMU_BUS1_SSS 148
> -#define CLK_GOUT_CMU_CIS_CLK0 149
> -#define CLK_GOUT_CMU_CIS_CLK1 150
> -#define CLK_GOUT_CMU_CIS_CLK2 151
> -#define CLK_GOUT_CMU_CIS_CLK3 152
> -#define CLK_GOUT_CMU_CIS_CLK4 153
> -#define CLK_GOUT_CMU_CIS_CLK5 154
> -#define CLK_GOUT_CMU_CORE_BUS 155
> -#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 156
> -#define CLK_GOUT_CMU_CPUCL0_SWITCH 157
> -#define CLK_GOUT_CMU_CPUCL1_SWITCH 158
> -#define CLK_GOUT_CMU_CPUCL2_BUSP 159
> -#define CLK_GOUT_CMU_CPUCL2_SWITCH 160
> -#define CLK_GOUT_CMU_CSIS_BUS 161
> -#define CLK_GOUT_CMU_CSIS_OIS_MCU 162
> -#define CLK_GOUT_CMU_DNC_BUS 163
> -#define CLK_GOUT_CMU_DNC_BUSM 164
> -#define CLK_GOUT_CMU_DNS_BUS 165
> -#define CLK_GOUT_CMU_DPU 166
> -#define CLK_GOUT_CMU_DPU_BUS 167
> -#define CLK_GOUT_CMU_DSP_BUS 168
> -#define CLK_GOUT_CMU_G2D_G2D 169
> -#define CLK_GOUT_CMU_G2D_MSCL 170
> -#define CLK_GOUT_CMU_G3D_SWITCH 171
> -#define CLK_GOUT_CMU_HPM 172
> -#define CLK_GOUT_CMU_HSI0_BUS 173
> -#define CLK_GOUT_CMU_HSI0_DPGTC 174
> -#define CLK_GOUT_CMU_HSI0_USB31DRD 175
> -#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 176
> -#define CLK_GOUT_CMU_HSI1_BUS 177
> -#define CLK_GOUT_CMU_HSI1_MMC_CARD 178
> -#define CLK_GOUT_CMU_HSI1_PCIE 179
> -#define CLK_GOUT_CMU_HSI1_UFS_CARD 180
> -#define CLK_GOUT_CMU_HSI1_UFS_EMBD 181
> -#define CLK_GOUT_CMU_HSI2_BUS 182
> -#define CLK_GOUT_CMU_HSI2_PCIE 183
> -#define CLK_GOUT_CMU_IPP_BUS 184
> -#define CLK_GOUT_CMU_ITP_BUS 185
> -#define CLK_GOUT_CMU_MCSC_BUS 186
> -#define CLK_GOUT_CMU_MCSC_GDC 187
> -#define CLK_GOUT_CMU_MFC0_MFC0 188
> -#define CLK_GOUT_CMU_MFC0_WFD 189
> -#define CLK_GOUT_CMU_MIF_BUSP 190
> -#define CLK_GOUT_CMU_NPU_BUS 191
> -#define CLK_GOUT_CMU_PERIC0_BUS 192
> -#define CLK_GOUT_CMU_PERIC0_IP 193
> -#define CLK_GOUT_CMU_PERIC1_BUS 194
> -#define CLK_GOUT_CMU_PERIC1_IP 195
> -#define CLK_GOUT_CMU_PERIS_BUS 196
> -#define CLK_GOUT_CMU_SSP_BUS 197
> -#define CLK_GOUT_CMU_TNR_BUS 198
> -#define CLK_GOUT_CMU_VRA_BUS 199
> +#define CLK_FOUT_G3D_PLL 1
> +#define CLK_FOUT_MMC_PLL 2
> +#define CLK_FOUT_SHARED0_PLL 3
> +#define CLK_FOUT_SHARED1_PLL 4
> +#define CLK_FOUT_SHARED2_PLL 5
> +#define CLK_FOUT_SHARED3_PLL 6
> +#define CLK_FOUT_SHARED4_PLL 7
> +#define CLK_MOUT_PLL_G3D 8
> +#define CLK_MOUT_PLL_MMC 9
> +#define CLK_MOUT_PLL_SHARED0 10
> +#define CLK_MOUT_PLL_SHARED1 11
> +#define CLK_MOUT_PLL_SHARED2 12
> +#define CLK_MOUT_PLL_SHARED3 13
> +#define CLK_MOUT_PLL_SHARED4 14
> +#define CLK_MOUT_CMU_DPU_BUS 15
> +#define CLK_MOUT_CMU_APM_BUS 16
> +#define CLK_MOUT_CMU_AUD_CPU 17
> +#define CLK_MOUT_CMU_BUS0_BUS 18
> +#define CLK_MOUT_CMU_BUS1_BUS 19
> +#define CLK_MOUT_CMU_BUS1_SSS 20
> +#define CLK_MOUT_CMU_CIS_CLK0 21
> +#define CLK_MOUT_CMU_CIS_CLK1 22
> +#define CLK_MOUT_CMU_CIS_CLK2 23
> +#define CLK_MOUT_CMU_CIS_CLK3 24
> +#define CLK_MOUT_CMU_CIS_CLK4 25
> +#define CLK_MOUT_CMU_CIS_CLK5 26
> +#define CLK_MOUT_CMU_CMU_BOOST 27
> +#define CLK_MOUT_CMU_CORE_BUS 28
> +#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 29
> +#define CLK_MOUT_CMU_CPUCL0_SWITCH 30
> +#define CLK_MOUT_CMU_CPUCL1_SWITCH 31
> +#define CLK_MOUT_CMU_CPUCL2_BUSP 32
> +#define CLK_MOUT_CMU_CPUCL2_SWITCH 33
> +#define CLK_MOUT_CMU_CSIS_BUS 34
> +#define CLK_MOUT_CMU_CSIS_OIS_MCU 35
> +#define CLK_MOUT_CMU_DNC_BUS 36
> +#define CLK_MOUT_CMU_DNC_BUSM 37
> +#define CLK_MOUT_CMU_DNS_BUS 38
> +#define CLK_MOUT_CMU_DPU 39
> +#define CLK_MOUT_CMU_DPU_ALT 40
> +#define CLK_MOUT_CMU_DSP_BUS 41
> +#define CLK_MOUT_CMU_G2D_G2D 42
> +#define CLK_MOUT_CMU_G2D_MSCL 43
> +#define CLK_MOUT_CMU_HPM 44
> +#define CLK_MOUT_CMU_HSI0_BUS 45
> +#define CLK_MOUT_CMU_HSI0_DPGTC 46
> +#define CLK_MOUT_CMU_HSI0_USB31DRD 47
> +#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 48
> +#define CLK_MOUT_CMU_HSI1_BUS 49
> +#define CLK_MOUT_CMU_HSI1_MMC_CARD 50
> +#define CLK_MOUT_CMU_HSI1_PCIE 51
> +#define CLK_MOUT_CMU_HSI1_UFS_CARD 52
> +#define CLK_MOUT_CMU_HSI1_UFS_EMBD 53
> +#define CLK_MOUT_CMU_HSI2_BUS 54
> +#define CLK_MOUT_CMU_HSI2_PCIE 55
> +#define CLK_MOUT_CMU_IPP_BUS 56
> +#define CLK_MOUT_CMU_ITP_BUS 57
> +#define CLK_MOUT_CMU_MCSC_BUS 58
> +#define CLK_MOUT_CMU_MCSC_GDC 59
> +#define CLK_MOUT_CMU_CMU_BOOST_CPU 60
> +#define CLK_MOUT_CMU_MFC0_MFC0 61
> +#define CLK_MOUT_CMU_MFC0_WFD 62
> +#define CLK_MOUT_CMU_MIF_BUSP 63
> +#define CLK_MOUT_CMU_MIF_SWITCH 64
> +#define CLK_MOUT_CMU_NPU_BUS 65
> +#define CLK_MOUT_CMU_PERIC0_BUS 66
> +#define CLK_MOUT_CMU_PERIC0_IP 67
> +#define CLK_MOUT_CMU_PERIC1_BUS 68
> +#define CLK_MOUT_CMU_PERIC1_IP 69
> +#define CLK_MOUT_CMU_PERIS_BUS 70
> +#define CLK_MOUT_CMU_SSP_BUS 71
> +#define CLK_MOUT_CMU_TNR_BUS 72
> +#define CLK_MOUT_CMU_VRA_BUS 73
> +#define CLK_MOUT_CMU_CMUREF 74
> +#define CLK_MOUT_CMU_CLK_CMUREF 75
> +#define CLK_DOUT_CMU_APM_BUS 76
> +#define CLK_DOUT_CMU_AUD_CPU 77
> +#define CLK_DOUT_CMU_BUS0_BUS 78
> +#define CLK_DOUT_CMU_BUS1_BUS 79
> +#define CLK_DOUT_CMU_BUS1_SSS 80
> +#define CLK_DOUT_CMU_CIS_CLK0 81
> +#define CLK_DOUT_CMU_CIS_CLK1 82
> +#define CLK_DOUT_CMU_CIS_CLK2 83
> +#define CLK_DOUT_CMU_CIS_CLK3 84
> +#define CLK_DOUT_CMU_CIS_CLK4 85
> +#define CLK_DOUT_CMU_CIS_CLK5 86
> +#define CLK_DOUT_CMU_CMU_BOOST 87
> +#define CLK_DOUT_CMU_CORE_BUS 88
> +#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 89
> +#define CLK_DOUT_CMU_CPUCL0_SWITCH 90
> +#define CLK_DOUT_CMU_CPUCL1_SWITCH 91
> +#define CLK_DOUT_CMU_CPUCL2_BUSP 92
> +#define CLK_DOUT_CMU_CPUCL2_SWITCH 93
> +#define CLK_DOUT_CMU_CSIS_BUS 94
> +#define CLK_DOUT_CMU_CSIS_OIS_MCU 95
> +#define CLK_DOUT_CMU_DNC_BUS 96
> +#define CLK_DOUT_CMU_DNC_BUSM 97
> +#define CLK_DOUT_CMU_DNS_BUS 98
> +#define CLK_DOUT_CMU_DSP_BUS 99
> +#define CLK_DOUT_CMU_G2D_G2D 100
> +#define CLK_DOUT_CMU_G2D_MSCL 101
> +#define CLK_DOUT_CMU_G3D_SWITCH 102
> +#define CLK_DOUT_CMU_HPM 103
> +#define CLK_DOUT_CMU_HSI0_BUS 104
> +#define CLK_DOUT_CMU_HSI0_DPGTC 105
> +#define CLK_DOUT_CMU_HSI0_USB31DRD 106
> +#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 107
> +#define CLK_DOUT_CMU_HSI1_BUS 108
> +#define CLK_DOUT_CMU_HSI1_MMC_CARD 109
> +#define CLK_DOUT_CMU_HSI1_PCIE 110
> +#define CLK_DOUT_CMU_HSI1_UFS_CARD 111
> +#define CLK_DOUT_CMU_HSI1_UFS_EMBD 112
> +#define CLK_DOUT_CMU_HSI2_BUS 113
> +#define CLK_DOUT_CMU_HSI2_PCIE 114
> +#define CLK_DOUT_CMU_IPP_BUS 115
> +#define CLK_DOUT_CMU_ITP_BUS 116
> +#define CLK_DOUT_CMU_MCSC_BUS 117
> +#define CLK_DOUT_CMU_MCSC_GDC 118
> +#define CLK_DOUT_CMU_CMU_BOOST_CPU 119
> +#define CLK_DOUT_CMU_MFC0_MFC0 120
> +#define CLK_DOUT_CMU_MFC0_WFD 121
> +#define CLK_DOUT_CMU_MIF_BUSP 122
> +#define CLK_DOUT_CMU_NPU_BUS 123
> +#define CLK_DOUT_CMU_OTP 124
> +#define CLK_DOUT_CMU_PERIC0_BUS 125
> +#define CLK_DOUT_CMU_PERIC0_IP 126
> +#define CLK_DOUT_CMU_PERIC1_BUS 127
> +#define CLK_DOUT_CMU_PERIC1_IP 128
> +#define CLK_DOUT_CMU_PERIS_BUS 129
> +#define CLK_DOUT_CMU_SSP_BUS 130
> +#define CLK_DOUT_CMU_TNR_BUS 131
> +#define CLK_DOUT_CMU_VRA_BUS 132
> +#define CLK_DOUT_CMU_DPU 133
> +#define CLK_DOUT_CMU_DPU_ALT 134
> +#define CLK_DOUT_CMU_CLK_CMUREF 135
> +#define CLK_DOUT_CMU_SHARED0_DIV2 136
> +#define CLK_DOUT_CMU_SHARED0_DIV3 137
> +#define CLK_DOUT_CMU_SHARED0_DIV4 138
> +#define CLK_DOUT_CMU_SHARED1_DIV2 139
> +#define CLK_DOUT_CMU_SHARED1_DIV3 140
> +#define CLK_DOUT_CMU_SHARED1_DIV4 141
> +#define CLK_DOUT_CMU_SHARED2_DIV2 142
> +#define CLK_DOUT_CMU_SHARED4_DIV2 145
> +#define CLK_DOUT_CMU_SHARED4_DIV3 146
> +#define CLK_DOUT_CMU_SHARED4_DIV4 147
> +#define CLK_GOUT_CMU_G3D_BUS 148
> +#define CLK_GOUT_CMU_MIF_SWITCH 149
> +#define CLK_GOUT_CMU_APM_BUS 150
> +#define CLK_GOUT_CMU_AUD_CPU 151
> +#define CLK_GOUT_CMU_BUS0_BUS 152
> +#define CLK_GOUT_CMU_BUS1_BUS 153
> +#define CLK_GOUT_CMU_BUS1_SSS 154
> +#define CLK_GOUT_CMU_CIS_CLK0 155
> +#define CLK_GOUT_CMU_CIS_CLK1 156
> +#define CLK_GOUT_CMU_CIS_CLK2 157
> +#define CLK_GOUT_CMU_CIS_CLK3 158
> +#define CLK_GOUT_CMU_CIS_CLK4 159
> +#define CLK_GOUT_CMU_CIS_CLK5 160
> +#define CLK_GOUT_CMU_CORE_BUS 161
> +#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 162
> +#define CLK_GOUT_CMU_CPUCL0_SWITCH 163
> +#define CLK_GOUT_CMU_CPUCL1_SWITCH 164
> +#define CLK_GOUT_CMU_CPUCL2_BUSP 165
> +#define CLK_GOUT_CMU_CPUCL2_SWITCH 166
> +#define CLK_GOUT_CMU_CSIS_BUS 167
> +#define CLK_GOUT_CMU_CSIS_OIS_MCU 168
> +#define CLK_GOUT_CMU_DNC_BUS 169
> +#define CLK_GOUT_CMU_DNC_BUSM 170
> +#define CLK_GOUT_CMU_DNS_BUS 171
> +#define CLK_GOUT_CMU_DPU 172
> +#define CLK_GOUT_CMU_DPU_BUS 173
> +#define CLK_GOUT_CMU_DSP_BUS 174
> +#define CLK_GOUT_CMU_G2D_G2D 175
> +#define CLK_GOUT_CMU_G2D_MSCL 176
> +#define CLK_GOUT_CMU_G3D_SWITCH 177
> +#define CLK_GOUT_CMU_HPM 178
> +#define CLK_GOUT_CMU_HSI0_BUS 179
> +#define CLK_GOUT_CMU_HSI0_DPGTC 180
> +#define CLK_GOUT_CMU_HSI0_USB31DRD 181
> +#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 182
> +#define CLK_GOUT_CMU_HSI1_BUS 183
> +#define CLK_GOUT_CMU_HSI1_MMC_CARD 184
> +#define CLK_GOUT_CMU_HSI1_PCIE 185
> +#define CLK_GOUT_CMU_HSI1_UFS_CARD 186
> +#define CLK_GOUT_CMU_HSI1_UFS_EMBD 187
> +#define CLK_GOUT_CMU_HSI2_BUS 188
> +#define CLK_GOUT_CMU_HSI2_PCIE 189
> +#define CLK_GOUT_CMU_IPP_BUS 190
> +#define CLK_GOUT_CMU_ITP_BUS 191
> +#define CLK_GOUT_CMU_MCSC_BUS 192
> +#define CLK_GOUT_CMU_MCSC_GDC 193
> +#define CLK_GOUT_CMU_MFC0_MFC0 194
> +#define CLK_GOUT_CMU_MFC0_WFD 195
> +#define CLK_GOUT_CMU_MIF_BUSP 196
> +#define CLK_GOUT_CMU_NPU_BUS 197
> +#define CLK_GOUT_CMU_PERIC0_BUS 198
> +#define CLK_GOUT_CMU_PERIC0_IP 199
> +#define CLK_GOUT_CMU_PERIC1_BUS 200
> +#define CLK_GOUT_CMU_PERIC1_IP 201
> +#define CLK_GOUT_CMU_PERIS_BUS 202
> +#define CLK_GOUT_CMU_SSP_BUS 203
> +#define CLK_GOUT_CMU_TNR_BUS 204
> +#define CLK_GOUT_CMU_VRA_BUS 205
>
> /* CMU_HSI0 */
> #define CLK_MOUT_HSI0_BUS_USER 1
>
> --
> 2.49.0
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend
2025-08-20 19:29 ` Conor Dooley
@ 2025-08-23 17:27 ` Denzeel Oliva
2025-08-24 8:16 ` Krzysztof Kozlowski
0 siblings, 1 reply; 7+ messages in thread
From: Denzeel Oliva @ 2025-08-23 17:27 UTC (permalink / raw)
To: Conor Dooley
Cc: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, linux-samsung-soc, linux-clk, linux-arm-kernel,
linux-kernel, devicetree
> This looks like a massive ABI break, where is the justification for
> doing it?
>
> Cheers,
> Conor.
Hi Conor,
I reordered because the current IDs don’t match CMU_TOP:
the PLL mux select is in PLL_CON0, not CON3, which gave wrong/low rates.
I also added DPU/CMUREF and a missing fixed-factor path to stop bad rates
and clk_summary hangs on hardware.
I’d rather fix the mapping now than keep a wrong layout.
Thanks,
Denzeel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend
2025-08-23 17:27 ` Denzeel Oliva
@ 2025-08-24 8:16 ` Krzysztof Kozlowski
0 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2025-08-24 8:16 UTC (permalink / raw)
To: Denzeel Oliva, Conor Dooley
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, linux-samsung-soc,
linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 23/08/2025 19:27, Denzeel Oliva wrote:
>> This looks like a massive ABI break, where is the justification for
>> doing it?
>>
>> Cheers,
>> Conor.
>
> Hi Conor,
>
> I reordered because the current IDs don’t match CMU_TOP:
> the PLL mux select is in PLL_CON0, not CON3, which gave wrong/low rates.
IDs are abstract, they cannot give wrong/low rates.
> I also added DPU/CMUREF and a missing fixed-factor path to stop bad rates
> and clk_summary hangs on hardware.
Not really related to ABI.
None of these justify changing the ABI or I don't understand the problem
at all.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-08-24 8:19 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-20 14:57 [PATCH v2 0/3] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
2025-08-20 14:57 ` [PATCH v2 1/3] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
2025-08-20 14:57 ` [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend Denzeel Oliva
2025-08-20 19:29 ` Conor Dooley
2025-08-23 17:27 ` Denzeel Oliva
2025-08-24 8:16 ` Krzysztof Kozlowski
2025-08-20 14:57 ` [PATCH v2 3/3] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Denzeel Oliva
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