[PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

[PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

[Icenowy Zheng]

Allwinner H3 have a its USB PHY0 routed to two USB controllers: one is
a MUSB controller, which can work in peripheral mode, but works badly in
host mode (several hardware will fail on the MUSB controller, even connect
one MUSB controller in peripheral mode to another one in host mode cannot
work); the other is a pair of EHCI/OHCI controller, which can work only
in host mode, but have better compatibillity. The route is controlled in
a register, which we have set it to HCI only when we do not know about
it well.

Add support to route to the best controller according to current USB mode
(host/peripheral).

Note: Currently even if hardware only support hostmode, we should still
enable the MUSB controller, as it controls the USB mode. (Some this kind
of hardware can also work in peripheral mode by settings in the sysfs
node of MUSB, then connect it to another host via a USB Type-A to Type-A
cable.)

Patch 1 changes the device tree binding to include the "pmu0" for HCI pair.

Patch 2 adds support for auto routing of PHY0. It's currently only enabled
on H3, but it's easy to extend it to other SoCs which feature this
route control.

Patch 3 adds necessary device tree nodes to the H3 DTSI file. Note: The
phy is not bind for OHCI/EHCI0, as OHCI/EHCI drivers will keep the VBUS
on. Only MUSB driver can properly handle a dual-role PHY.

Patch 4 enables USB OTG functionality on Orange Pi One board, which is
the only H3 board I have that have proper OTG function. It's easy to
enable OTG on other boards with their schematics.

Patch 5 enables USB OTG functionality on Orange Pi Zero board, as the
board cannot output power on Vbus, I only enabled peripheral mode by
default.

The USB PHY on V3s/A64 SoCs also feature this capability, and it will
be soon enabled on these SoCs after this patchset is merged.

Icenowy Zheng (5):
  dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
  phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI
  ARM: dts: sun8i: h3: add usb_otg and OHCI/EHCI for usbc0 on H3
  ARM: dts: sun8i: h3: enable USB OTG on Orange Pi One
  ARM: dts: sun8i: h2+: enable USB OTG for Orange Pi Zero board

 .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  1 +
 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts  | 14 ++++++
 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts        | 22 +++++++++-
 arch/arm/boot/dts/sun8i-h3.dtsi                    | 32 ++++++++++++++
 drivers/phy/phy-sun4i-usb.c                        | 50 ++++++++++++++--------
 5 files changed, 101 insertions(+), 18 deletions(-)

-- 
2.11.1

[PATCH v3 1/5] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

[Icenowy Zheng]

Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.

When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.

Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
New patch in v3.

 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index e42334258185..005bc22938ff 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -15,6 +15,7 @@ Required properties:
 - reg : a list of offset + length pairs
 - reg-names :
   * "phy_ctrl"
+  * "pmu0" for H3, V3s and A64
   * "pmu1"
   * "pmu2" for sun4i, sun6i or sun7i
 - #phy-cells : from the generic phy bindings, must be 1
-- 
2.11.1

[linux-sunxi] [PATCH v3 1/5] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

[Chen-Yu Tsai]

On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
> controllers: one is MUSB and the other is a EHCI/OHCI pair.
>
> When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
> tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
>
> Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v3 2/5] phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI

[Icenowy Zheng]

On newer Allwinner SoCs (H3 and after), the PHY0 node is routed to both
MUSB controller for peripheral and host support (the host support is
slightly broken), and a pair of EHCI/OHCI controllers, which provide a
better support for host mode.

Add support for automatically switch the route of PHY0 according to the
status of dr_mode and id det pin.

Only H3 have this function enabled in this patch, as further SoCs will
be tested later and then have it enabled.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
Changes in v3:
- Add Chen-Yu's ACK. (I made a patch 1 that changes dt binding)
Changes in v2:
- Re-route after force session end.
- Drop id_det based on role code in reroute function, as we already
  properly set id_det in id_det getting function.

 drivers/phy/phy-sun4i-usb.c | 50 ++++++++++++++++++++++++++++++---------------
 1 file changed, 33 insertions(+), 17 deletions(-)

diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index a21b5f24a340..b4458878ece7 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -49,12 +49,14 @@
 #define REG_PHYBIST			0x08
 #define REG_PHYTUNE			0x0c
 #define REG_PHYCTL_A33			0x10
-#define REG_PHY_UNK_H3			0x20
+#define REG_PHY_OTGCTL			0x20
 
 #define REG_PMU_UNK1			0x10
 
 #define PHYCTL_DATA			BIT(7)
 
+#define OTGCTL_ROUTE_MUSB		BIT(0)
+
 #define SUNXI_AHB_ICHR8_EN		BIT(10)
 #define SUNXI_AHB_INCR4_BURST_EN	BIT(9)
 #define SUNXI_AHB_INCRX_ALIGN_EN	BIT(8)
@@ -110,6 +112,7 @@ struct sun4i_usb_phy_cfg {
 	u8 phyctl_offset;
 	bool dedicated_clocks;
 	bool enable_pmu_unk1;
+	bool phy0_dual_route;
 };
 
 struct sun4i_usb_phy_data {
@@ -271,23 +274,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 		writel(val & ~2, phy->pmu + REG_PMU_UNK1);
 	}
 
-	if (data->cfg->type == sun8i_h3_phy) {
-		if (phy->index == 0) {
-			val = readl(data->base + REG_PHY_UNK_H3);
-			writel(val & ~1, data->base + REG_PHY_UNK_H3);
-		}
-	} else {
-		/* Enable USB 45 Ohm resistor calibration */
-		if (phy->index == 0)
-			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+	/* Enable USB 45 Ohm resistor calibration */
+	if (phy->index == 0)
+		sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
 
-		/* Adjust PHY's magnitude and rate */
-		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+	/* Adjust PHY's magnitude and rate */
+	sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
 
-		/* Disconnect threshold adjustment */
-		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
-				    data->cfg->disc_thresh, 2);
-	}
+	/* Disconnect threshold adjustment */
+	sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+			    data->cfg->disc_thresh, 2);
 
 	sun4i_usb_phy_passby(phy, 1);
 
@@ -486,6 +482,21 @@ static const struct phy_ops sun4i_usb_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
+{
+	u32 regval;
+
+	regval = readl(data->base + REG_PHY_OTGCTL);
+	if (id_det == 0) {
+		/* Host mode. Route phy0 to EHCI/OHCI */
+		regval &= ~OTGCTL_ROUTE_MUSB;
+	} else {
+		/* Peripheral mode. Route phy0 to MUSB */
+		regval |= OTGCTL_ROUTE_MUSB;
+	}
+	writel(regval, data->base + REG_PHY_OTGCTL);
+}
+
 static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
 {
 	struct sun4i_usb_phy_data *data =
@@ -546,6 +557,10 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
 			sun4i_usb_phy0_set_vbus_detect(phy0, 1);
 			mutex_unlock(&phy0->mutex);
 		}
+
+		/* Re-route PHY0 if necessary */
+		if (data->cfg->phy0_dual_route)
+			sun4i_usb_phy0_reroute(data, id_det);
 	}
 
 	if (vbus_notify)
@@ -700,7 +715,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 			return PTR_ERR(phy->reset);
 		}
 
-		if (i) { /* No pmu for usbc0 */
+		if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
 			snprintf(name, sizeof(name), "pmu%d", i);
 			res = platform_get_resource_byname(pdev,
 							IORESOURCE_MEM, name);
@@ -825,6 +840,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.disc_thresh = 3,
 	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
+	.phy0_dual_route = true,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
-- 
2.11.1

[PATCH v3 3/5] ARM: dts: sun8i: h3: add usb_otg and OHCI/EHCI for usbc0 on H3

[Icenowy Zheng]

Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
or MUSB controller.

Add device nodes for these controllers.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v3:
- Add "h3:" to commit message.

 arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 27780b97c863..e8265ba68952 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -206,6 +206,19 @@
 			#size-cells = <0>;
 		};
 
+		usb_otg: usb at 01c19000 {
+			compatible = "allwinner,sun8i-h3-musb";
+			reg = <0x01c19000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			status = "disabled";
+		};
+
 		usbphy: phy at 01c19400 {
 			compatible = "allwinner,sun8i-h3-usb-phy";
 			reg = <0x01c19400 0x2c>,
@@ -238,6 +251,25 @@
 			#phy-cells = <1>;
 		};
 
+		ehci0: usb at 01c1a000 {
+			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+			reg = <0x01c1a000 0x100>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
+		ohci0: usb at 01c1a400 {
+			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+			reg = <0x01c1a400 0x100>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
 		ehci1: usb at 01c1b000 {
 			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 			reg = <0x01c1b000 0x100>;
-- 
2.11.1

[linux-sunxi] [PATCH v3 3/5] ARM: dts: sun8i: h3: add usb_otg and OHCI/EHCI for usbc0 on H3

[Chen-Yu Tsai]

On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
> or MUSB controller.
>
> Add device nodes for these controllers.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v3 4/5] ARM: dts: sun8i: h3: enable USB OTG on Orange Pi One

[Icenowy Zheng]

Orange Pi One features a MicroUSB port that can work in both host mode
and peripheral mode.

When in host mode, its VBUS is controlled via a GPIO; when in peripheral
mode, its VBUS cannot be used to power up the board.

Add support for this port.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v3:
- Add "h3:" in commit message.

 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 34da853ee037..b87778d74239 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -90,6 +90,10 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -104,6 +108,10 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
 &ohci1 {
 	status = "okay";
 };
@@ -127,6 +135,11 @@
 	};
 };
 
+&reg_usb0_vbus {
+	gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
@@ -151,7 +164,14 @@
 	status = "disabled";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
-	/* USB VBUS is always on */
+	/* USB Type-A port's VBUS is always on */
+	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
 	status = "okay";
 };
-- 
2.11.1

[linux-sunxi] [PATCH v3 4/5] ARM: dts: sun8i: h3: enable USB OTG on Orange Pi One

[Chen-Yu Tsai]

On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> Orange Pi One features a MicroUSB port that can work in both host mode
> and peripheral mode.
>
> When in host mode, its VBUS is controlled via a GPIO; when in peripheral
> mode, its VBUS cannot be used to power up the board.
>
> Add support for this port.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v3 5/5] ARM: dts: sun8i: h2+: enable USB OTG for Orange Pi Zero board

[Icenowy Zheng]

Orange Pi Zero board features a USB OTG port, which has a ID pin, and
can be used to power up the board. However, even if the board is powered
via +5V pin in GPIO/expansion headers, the VBUS in the OTG port cannot
be powered up, thus it's impossible to use it in host mode with simple
OTG cables.

Add support for it in peripheral mode.

If someone really want to use it in host mode, the mode of PHY can be
switch via sysfs, then use a powered USB OTG cable or powered USB HUB to
power up external USB devices.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
New patch in v3.

 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b7ca916d871d..63f819394b98 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -96,6 +96,10 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -132,6 +136,10 @@
 	bias-pull-up;
 };
 
+&ohci0 {
+	status = "okay";
+};
+
 &ohci1 {
 	status = "okay";
 };
@@ -154,7 +162,13 @@
 	status = "disabled";
 };
 
+&usb_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
 &usbphy {
 	/* USB VBUS is always on */
 	status = "okay";
+	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
 };
-- 
2.11.1

[linux-sunxi] [PATCH v3 5/5] ARM: dts: sun8i: h2+: enable USB OTG for Orange Pi Zero board

[Chen-Yu Tsai]

Hi,

On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> Orange Pi Zero board features a USB OTG port, which has a ID pin, and
> can be used to power up the board. However, even if the board is powered
> via +5V pin in GPIO/expansion headers, the VBUS in the OTG port cannot
> be powered up, thus it's impossible to use it in host mode with simple
> OTG cables.
>
> Add support for it in peripheral mode.
>
> If someone really want to use it in host mode, the mode of PHY can be
> switch via sysfs, then use a powered USB OTG cable or powered USB HUB to
> power up external USB devices.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> New patch in v3.
>
>  arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> index b7ca916d871d..63f819394b98 100644
> --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> @@ -96,6 +96,10 @@
>         };
>  };
>
> +&ehci0 {
> +       status = "okay";
> +};
> +
>  &ehci1 {
>         status = "okay";
>  };
> @@ -132,6 +136,10 @@
>         bias-pull-up;
>  };
>
> +&ohci0 {
> +       status = "okay";
> +};
> +
>  &ohci1 {
>         status = "okay";
>  };
> @@ -154,7 +162,13 @@
>         status = "disabled";
>  };
>
> +&usb_otg {
> +       dr_mode = "peripheral";
> +       status = "okay";
> +};
> +
>  &usbphy {
>         /* USB VBUS is always on */

This comment does not match your commit message, which says it's always off.

ChenYu

>         status = "okay";
> +       usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
>  };
> --
> 2.11.1
>
> --
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[linux-sunxi] [PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

[Ondřej Jirman]

Hi Icenowy,

when I was trying to add OTG support I found an issue with powercycling.
When I have USB cable connecting PC and the OTG port on the SBC, when
the board enables the vbus, it would become impossible to power cycle
the board after poweroff. The reason being that when vbus is enabled,
the board is powered from the OTG port even if you disconnect the barrel
plug.

Should kernel turn off the vbus before shutting down/restarting? What do
you think?

regards,
  o.

Dne 6.3.2017 v 23:34 Icenowy Zheng napsal(a):
> Allwinner H3 have a its USB PHY0 routed to two USB controllers: one is
> a MUSB controller, which can work in peripheral mode, but works badly in
> host mode (several hardware will fail on the MUSB controller, even connect
> one MUSB controller in peripheral mode to another one in host mode cannot
> work); the other is a pair of EHCI/OHCI controller, which can work only
> in host mode, but have better compatibillity. The route is controlled in
> a register, which we have set it to HCI only when we do not know about
> it well.
> 
> Add support to route to the best controller according to current USB mode
> (host/peripheral).
> 
> Note: Currently even if hardware only support hostmode, we should still
> enable the MUSB controller, as it controls the USB mode. (Some this kind
> of hardware can also work in peripheral mode by settings in the sysfs
> node of MUSB, then connect it to another host via a USB Type-A to Type-A
> cable.)
> 
> Patch 1 changes the device tree binding to include the "pmu0" for HCI pair.
> 
> Patch 2 adds support for auto routing of PHY0. It's currently only enabled
> on H3, but it's easy to extend it to other SoCs which feature this
> route control.
> 
> Patch 3 adds necessary device tree nodes to the H3 DTSI file. Note: The
> phy is not bind for OHCI/EHCI0, as OHCI/EHCI drivers will keep the VBUS
> on. Only MUSB driver can properly handle a dual-role PHY.
> 
> Patch 4 enables USB OTG functionality on Orange Pi One board, which is
> the only H3 board I have that have proper OTG function. It's easy to
> enable OTG on other boards with their schematics.
> 
> Patch 5 enables USB OTG functionality on Orange Pi Zero board, as the
> board cannot output power on Vbus, I only enabled peripheral mode by
> default.
> 
> The USB PHY on V3s/A64 SoCs also feature this capability, and it will
> be soon enabled on these SoCs after this patchset is merged.
> 
> Icenowy Zheng (5):
>   dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
>   phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI
>   ARM: dts: sun8i: h3: add usb_otg and OHCI/EHCI for usbc0 on H3
>   ARM: dts: sun8i: h3: enable USB OTG on Orange Pi One
>   ARM: dts: sun8i: h2+: enable USB OTG for Orange Pi Zero board
> 
>  .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  1 +
>  arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts  | 14 ++++++
>  arch/arm/boot/dts/sun8i-h3-orangepi-one.dts        | 22 +++++++++-
>  arch/arm/boot/dts/sun8i-h3.dtsi                    | 32 ++++++++++++++
>  drivers/phy/phy-sun4i-usb.c                        | 50 ++++++++++++++--------
>  5 files changed, 101 insertions(+), 18 deletions(-)
> 

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[linux-sunxi] [PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

[Icenowy Zheng]

07.03.2017, 07:48, "Ond?ej Jirman" <megous@megous.com>:
> Hi Icenowy,
>
> when I was trying to add OTG support I found an issue with powercycling.
> When I have USB cable connecting PC and the OTG port on the SBC, when
> the board enables the vbus, it would become impossible to power cycle
> the board after poweroff. The reason being that when vbus is enabled,
> the board is powered from the OTG port even if you disconnect the barrel
> plug.
>
> Should kernel turn off the vbus before shutting down/restarting? What do
> you think?

It's a good problem.

I think this problem can be abstracted into:
Some regulators are needed to be shut down before system 
shutdown.

Is there any framework for it?

Mark,
I add you to recipients for the question above.

Thanks,
Icenowy

>
> regards,
> ??o.
>
> Dne 6.3.2017 v 23:34 Icenowy Zheng napsal(a):
>> ?Allwinner H3 have a its USB PHY0 routed to two USB controllers: one is
>> ?a MUSB controller, which can work in peripheral mode, but works badly in
>> ?host mode (several hardware will fail on the MUSB controller, even connect
>> ?one MUSB controller in peripheral mode to another one in host mode cannot
>> ?work); the other is a pair of EHCI/OHCI controller, which can work only
>> ?in host mode, but have better compatibillity. The route is controlled in
>> ?a register, which we have set it to HCI only when we do not know about
>> ?it well.
>>
>> ?Add support to route to the best controller according to current USB mode
>> ?(host/peripheral).
>>
>> ?Note: Currently even if hardware only support hostmode, we should still
>> ?enable the MUSB controller, as it controls the USB mode. (Some this kind
>> ?of hardware can also work in peripheral mode by settings in the sysfs
>> ?node of MUSB, then connect it to another host via a USB Type-A to Type-A
>> ?cable.)
>>
>> ?Patch 1 changes the device tree binding to include the "pmu0" for HCI pair.
>>
>> ?Patch 2 adds support for auto routing of PHY0. It's currently only enabled
>> ?on H3, but it's easy to extend it to other SoCs which feature this
>> ?route control.
>>
>> ?Patch 3 adds necessary device tree nodes to the H3 DTSI file. Note: The
>> ?phy is not bind for OHCI/EHCI0, as OHCI/EHCI drivers will keep the VBUS
>> ?on. Only MUSB driver can properly handle a dual-role PHY.
>>
>> ?Patch 4 enables USB OTG functionality on Orange Pi One board, which is
>> ?the only H3 board I have that have proper OTG function. It's easy to
>> ?enable OTG on other boards with their schematics.
>>
>> ?Patch 5 enables USB OTG functionality on Orange Pi Zero board, as the
>> ?board cannot output power on Vbus, I only enabled peripheral mode by
>> ?default.
>>
>> ?The USB PHY on V3s/A64 SoCs also feature this capability, and it will
>> ?be soon enabled on these SoCs after this patchset is merged.
>>
>> ?Icenowy Zheng (5):
>> ???dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
>> ???phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI
>> ???ARM: dts: sun8i: h3: add usb_otg and OHCI/EHCI for usbc0 on H3
>> ???ARM: dts: sun8i: h3: enable USB OTG on Orange Pi One
>> ???ARM: dts: sun8i: h2+: enable USB OTG for Orange Pi Zero board
>>
>> ??.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
>> ??arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 14 ++++++
>> ??arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 22 +++++++++-
>> ??arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++
>> ??drivers/phy/phy-sun4i-usb.c | 50 ++++++++++++++--------
>> ??5 files changed, 101 insertions(+), 18 deletions(-)

[linux-sunxi] [PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

[Chen-Yu Tsai]

On Tue, Mar 7, 2017 at 8:24 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
>
>
> 07.03.2017, 07:48, "Ond?ej Jirman" <megous@megous.com>:
>> Hi Icenowy,
>>
>> when I was trying to add OTG support I found an issue with powercycling.
>> When I have USB cable connecting PC and the OTG port on the SBC, when
>> the board enables the vbus, it would become impossible to power cycle
>> the board after poweroff. The reason being that when vbus is enabled,
>> the board is powered from the OTG port even if you disconnect the barrel
>> plug.
>>
>> Should kernel turn off the vbus before shutting down/restarting? What do
>> you think?
>
> It's a good problem.
>
> I think this problem can be abstracted into:
> Some regulators are needed to be shut down before system
> shutdown.

Sounds like the board is getting back-powered from VBUS through the enabled
current regulator. Given that you have it connected to the PC, which I assume
means peripheral mode, the bigger issue is why is VBUS enabled in peripheral
mode? It should never ever be so.


Regards
ChenYu

> Is there any framework for it?
>
> Mark,
> I add you to recipients for the question above.
>
> Thanks,
> Icenowy
>
>>
>> regards,
>>   o.
>>
>> Dne 6.3.2017 v 23:34 Icenowy Zheng napsal(a):
>>>  Allwinner H3 have a its USB PHY0 routed to two USB controllers: one is
>>>  a MUSB controller, which can work in peripheral mode, but works badly in
>>>  host mode (several hardware will fail on the MUSB controller, even connect
>>>  one MUSB controller in peripheral mode to another one in host mode cannot
>>>  work); the other is a pair of EHCI/OHCI controller, which can work only
>>>  in host mode, but have better compatibillity. The route is controlled in
>>>  a register, which we have set it to HCI only when we do not know about
>>>  it well.
>>>
>>>  Add support to route to the best controller according to current USB mode
>>>  (host/peripheral).
>>>
>>>  Note: Currently even if hardware only support hostmode, we should still
>>>  enable the MUSB controller, as it controls the USB mode. (Some this kind
>>>  of hardware can also work in peripheral mode by settings in the sysfs
>>>  node of MUSB, then connect it to another host via a USB Type-A to Type-A
>>>  cable.)
>>>
>>>  Patch 1 changes the device tree binding to include the "pmu0" for HCI pair.
>>>
>>>  Patch 2 adds support for auto routing of PHY0. It's currently only enabled
>>>  on H3, but it's easy to extend it to other SoCs which feature this
>>>  route control.
>>>
>>>  Patch 3 adds necessary device tree nodes to the H3 DTSI file. Note: The
>>>  phy is not bind for OHCI/EHCI0, as OHCI/EHCI drivers will keep the VBUS
>>>  on. Only MUSB driver can properly handle a dual-role PHY.
>>>
>>>  Patch 4 enables USB OTG functionality on Orange Pi One board, which is
>>>  the only H3 board I have that have proper OTG function. It's easy to
>>>  enable OTG on other boards with their schematics.
>>>
>>>  Patch 5 enables USB OTG functionality on Orange Pi Zero board, as the
>>>  board cannot output power on Vbus, I only enabled peripheral mode by
>>>  default.
>>>
>>>  The USB PHY on V3s/A64 SoCs also feature this capability, and it will
>>>  be soon enabled on these SoCs after this patchset is merged.
>>>
>>>  Icenowy Zheng (5):
>>>    dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
>>>    phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI
>>>    ARM: dts: sun8i: h3: add usb_otg and OHCI/EHCI for usbc0 on H3
>>>    ARM: dts: sun8i: h3: enable USB OTG on Orange Pi One
>>>    ARM: dts: sun8i: h2+: enable USB OTG for Orange Pi Zero board
>>>
>>>   .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
>>>   arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 14 ++++++
>>>   arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 22 +++++++++-
>>>   arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++
>>>   drivers/phy/phy-sun4i-usb.c | 50 ++++++++++++++--------
>>>   5 files changed, 101 insertions(+), 18 deletions(-)
>
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