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Fri, 11 Sep 2026 10:42:36 -0700 (PDT) X-Received: by 2002:a05:6a00:4ac6:b0:84e:89a:b8ec with SMTP id d2e1a72fcca58-86b31ef6e46mr7785156b3a.11.1789148556310; Fri, 11 Sep 2026 10:42:36 -0700 (PDT) Received: from [192.168.0.6] ([49.204.105.169]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-86b286c49d2sm1515413b3a.10.2026.09.11.10.42.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Sep 2026 10:42:35 -0700 (PDT) Message-ID: Date: Fri, 11 Sep 2026 23:12:28 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/9] i2c: qcom-geni: Vote for SE clock rate using OPP To: Konrad Dybcio , Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: mukesh.savaliya@oss.qualcomm.com, chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-7-091697dbeb02@oss.qualcomm.com> Content-Language: en-US From: Praveen Talari In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: krgujleGiEUoUN_FPhjW4SutrQx7yei1 X-Authority-Analysis: v=2.4 cv=PLmaavqC c=1 sm=1 tr=0 ts=6aa43d8d cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=KFINdI5Z0390/lZYonNNQw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=NZ9nq7LxGt4YLS7AZqcA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: krgujleGiEUoUN_FPhjW4SutrQx7yei1 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTExMDI0OCBTYWx0ZWRfX9PUsSveMUiWp nQLyYjqOcdPj+JpFOsvRShYi/JF5X/UzVKvrHj4kqhpj3AG53+ejmUceTPM4uoBaYAUNeSrh11L 7aSXs9njnKCmpbb2OXLryHs1P/KIli0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTExMDI0OCBTYWx0ZWRfX0jAp27njcE7/ X9D1pmkwHgu43pFCnuUKt9htlg54O1eiOmOqXeNsghhRgenWSRBYw7I9FbMEYT43TysQynTzz+B XCVuvIwa4VXBZGbRXAFpvwGmhh9ZYogcDDfOb1BW3SUNkubcGv+5OlCnsFcRU4eKl70zRFUi0dw eqwwBajRbVwt+faL6YfF8EAxoNmp14toEPhVTAq74Z0bHyBk7ickBB2RkYj+40cwEw+oqpB5oof 4RqFw4AMrtIStngNd1euvQheBCAGBqiEF1oFiaVTHdYM+San7tC690CQYYjFhNNuAxBO0WTcT7p yj9sVU95H6Vx1Y0kmoetiwyY3iw13YG1qd+LWQiFhKPMQ5OSkvi3qTX0UGljqbgnnTsazx+bfqi vMXf3kFI2yhTDv7RzKeXiLC+I5+GA+RLJT56xZvzu61OS71JMOsyasuIjSQowYhQDRsqBVzp/+A OI0GUf94MoTkyGTvVpA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-11_06,2026-09-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609110248 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260911_104239_285887_08EE6566 X-CRM114-Status: GOOD ( 20.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Konrad, On 04-09-2026 14:22, Konrad Dybcio wrote: > On 8/27/26 7:59 PM, Praveen Talari wrote: >> The I2C driver currently assumes a fixed source clock selection and always >> programs SE_GENI_CLK_SEL to 0, which is not sufficient when the controller >> needs to switch between different source clocks. >> >> Add the source clock index and frequency to the I2C clock map entries and >> use them while configuring the controller. Request the required >> source clock rate through dev_pm_opp_set_rate() and program SE_GENI_CLK_SEL >> with the matching source index. >> >> Signed-off-by: Praveen Talari >> --- > [...] > >> + dev_pm_opp_set_rate(dev, 0); > This and the below call are unnecessary, rate and enablement/disablement > of a clock are orthogonal operations Yes, you are correct. However, in this case the rate change is primarily used to satisfy the voltage/performance requirements associated with the selected source clock frequency rather than the clock enable/disable state itself. The runtime PM handling follows the same approach currently used by the SPI and UART GENI drivers, where the performance vote is restored during runtime resume and released during runtime suspend. Please let me know if I'm overlooking something here. Thanks, Praveen Talari > > Konrad > >> + >> return 0; >> } >> >> @@ -1236,6 +1249,12 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) >> int ret = 0; >> struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); >> >> + if (gi2c->clk_fld && gi2c->clk_fld->src_clk_freq) { >> + ret = dev_pm_opp_set_rate(dev, gi2c->clk_fld->src_clk_freq); >> + if (ret) >> + return ret; >> + } >> + >> if (gi2c->dev_data->power_on) { >> ret = gi2c->dev_data->power_on(&gi2c->se); >> if (ret) >>