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Mon, 16 Mar 2020 13:24:57 -0400 X-MC-Unique: Zh47tl5WOg-Nn-jxg_VU_w-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0168CCF12C; Mon, 16 Mar 2020 17:10:27 +0000 (UTC) Received: from [10.36.118.12] (ovpn-118-12.ams2.redhat.com [10.36.118.12]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5FCEC5C1B2; Mon, 16 Mar 2020 17:10:22 +0000 (UTC) Subject: Re: [PATCH v5 02/23] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors To: Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200304203330.4967-1-maz@kernel.org> <20200304203330.4967-3-maz@kernel.org> From: Auger Eric Message-ID: Date: Mon, 16 Mar 2020 18:10:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20200304203330.4967-3-maz@kernel.org> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200316_102505_550856_40A99217 X-CRM114-Status: GOOD ( 18.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Jason Cooper , Suzuki K Poulose , Robert Richter , James Morse , Zenghui Yu , Thomas Gleixner , Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc On 3/4/20 9:33 PM, Marc Zyngier wrote: > In a system that is only sparsly populated with CPUs, we can end-up with sparsely > redistributors structures that are not initialized. Let's make sure we redistributor structures > don't try and access those when iterating over them (in this case when > checking we have a L2 VPE table). > > Fixes: 4e6437f12d6e ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level") > Signed-off-by: Marc Zyngier > Reviewed-by: Zenghui Yu > --- > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > index 83b1186ffcad..da883a691028 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -2452,6 +2452,10 @@ static bool allocate_vpe_l2_table(int cpu, u32 id) > if (!gic_rdists->has_rvpeid) > return true; > > + /* Skip non-present CPUs */ > + if (!base) > + return true; > + > val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); > > esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1; > Reviewed-by: Eric Auger Eric _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel