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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXQOY-0004Q2-U0; Tue, 27 Oct 2020 14:56:18 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXQOV-0004P8-Hc for linux-arm-kernel@lists.infradead.org; Tue, 27 Oct 2020 14:56:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22AE913D5; Tue, 27 Oct 2020 07:56:13 -0700 (PDT) Received: from [172.16.1.113] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 91B7D3F719; Tue, 27 Oct 2020 07:56:11 -0700 (PDT) Subject: Re: [PATCH 04/11] KVM: arm64: Move PC rollback on SError to HYP To: Marc Zyngier References: <20201026133450.73304-1-maz@kernel.org> <20201026133450.73304-5-maz@kernel.org> From: James Morse Message-ID: Date: Tue, 27 Oct 2020 14:56:05 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20201026133450.73304-5-maz@kernel.org> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_105615_654091_4A579262 X-CRM114-Status: GOOD ( 19.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Suzuki K Poulose , kernel-team@android.com, Quentin Perret , Andrew Scull , David Brazdil , Will Deacon , kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 26/10/2020 13:34, Marc Zyngier wrote: > Instead of handling the "PC rollback on SError during HVC" at EL1 (which > requires disclosing PC to a potentially untrusted kernel), let's move > this fixup to ... fixup_guest_exit(), which is where we do all fixups. > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h > index d687e574cde5..668f02c7b0b3 100644 > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h > @@ -411,6 +411,21 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) > if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) > vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR); > > + if (ARM_SERROR_PENDING(*exit_code)) { > + u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); > + > + /* > + * HVC already have an adjusted PC, which we need to > + * correct in order to return to after having injected > + * the SError. > + * > + * SMC, on the other hand, is *trapped*, meaning its > + * preferred return address is the SMC itself. > + */ > + if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64) > + *vcpu_pc(vcpu) -= 4; Isn't *vcpu_pc(vcpu) the PC of the previous entry for this vcpu?.... its not the PC of the exit until __sysreg_save_el2_return_state() saves it, which happens just after fixup_guest_exit(). Mess with ELR_EL2 directly? Thanks, James > + } > + > /* > * We're using the raw exception code in order to only process > * the trap if no SError is pending. We will come back to the > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel