From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D168DC55184 for ; Tue, 4 Aug 2026 02:44:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=gpT1FAd/Ou6ubtzqCbG7hgWwpUpLT83GDnqC3oQIUbw=; b=zZLD7dPrvZq0SuSqlWPOEqgcFv XAlLJfATUt2Ei2wTOgBI2VXTx5gtYh/p7n9nSuDrpGdZBtDW5/IOlXGkNFECCIoFFYHvmTrPx2pws rxfgJSpmuYAVo2+q9le6J1LQQPJ/naUPAZqiE51xUhRkuQp7Dqwkuge3hNUFQm/+ypBUwZN/jkd1c 71C5G2WQKzmd7Y81Bl+zqbaALslOlD38EFdj94dCyctJ0fmU24hxRPy0Hw4p11aOe0Z28fFowrpcK loyYsQEhLKa7j5OMoTR0U8IJMz7SpzAQCwWyW+FWPnnCHJS7yz02XAfjIQobw7eEanmNafzyww25r gehDmh+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wr58N-00000000rNn-3kET; Tue, 04 Aug 2026 02:44:03 +0000 Received: from vps0.lunn.ch ([156.67.10.101]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wr58L-00000000rMz-1fQW for linux-arm-kernel@lists.infradead.org; Tue, 04 Aug 2026 02:44:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=gpT1FAd/Ou6ubtzqCbG7hgWwpUpLT83GDnqC3oQIUbw=; b=diW6+82fctwCE+HQww2Ii6cSFa a9Dm8AJVjUmp34KLNiqKnGXkM7uPqxSOYXOT28SGPhOTj/mRWVpM7Aa6bCbxIGpTpvZJJLKAcd9O6 udhLuhcNwpH7BsYXEucYFyba838Qecm9z1viQPUP64bvcUe7jCQhAUSduK7ad9k38aaM=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1wr58A-00FtgY-3f; Tue, 04 Aug 2026 04:43:50 +0200 Date: Tue, 4 Aug 2026 04:43:50 +0200 From: Andrew Lunn To: Andre Przywara Cc: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Heiner Kallweit , Russell King , Liu Changjie , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/6] net: phy: maxio: parse and enable PHY clock from generic DT binding Message-ID: References: <20260803101452.2993721-1-andre.przywara@arm.com> <20260803101452.2993721-3-andre.przywara@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260803101452.2993721-3-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260803_194401_434366_CC8967D5 X-CRM114-Status: GOOD ( 14.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 03, 2026 at 12:14:48PM +0200, Andre Przywara wrote: > The generic PHY DT binding features a clocks property, which describes > the clock input to the PHY. Typically this is a crystal oscillator, so > it works without software interaction. But some boards want to save some > pennies on that part, and let a clock fanout pin from the SoC provide this > clock signal. In this case the PHY probe routine needs to enable this > clock explicitly. > > Look for a "clocks" property inside the PHY node and enable that clock, > if one is provided. > > This allows boards with a SoC-driven PHY clock to use the PHY. Please > note that without the clock enabled, the PHY will not be detected on the > MDIO bus, so the PHY-ID needs to be explicitly named in the PHY > compatible string: > compatible = "ethernet-phy-id7b74.4411"; > > Signed-off-by: Andre Przywara Reviewed-by: Andrew Lunn Andrew