* [PATCH v3 0/5] Introduce support for Exynos7870 clocks and PMU
@ 2025-02-18 18:50 Kaustabh Chakraborty
2025-02-18 18:50 ` [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU Kaustabh Chakraborty
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-18 18:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, Kaustabh Chakraborty
Add a CMU driver for Exynos7870 devices. It handles the following
clock banks:
* CMU_MIF
* CMU_DISPAUD
* CMU_FSYS
* CMU_G3D
* CMU_ISP
* CMU_MFCMSCL
* CMU_PERI
It also documents Exynos7870 PMU's compatible, and adds a CLKOUT driver
which depends on the compatible. The CLKOUT driver manages clocks from
PMU_DEBUG.
This patch series is a part of Exynos7870 upstreaming.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
Changes in v3:
- Fix incorrect versioning (Link to v2: is labelled as v1).
- Fix formatting issues in clk-exynos7870 DT docs (from v1).
- Add myself as maintainer for clk-exynos7870.
- Change clock name definitions in clk-exynos7870 DT docs.
- Fix line wrapping in commit message of exynos7870-pmu DT docs.
- Change a few ordinals of PERI* clocks in the clk-exynos7870 driver.
- Take over ownership of patches by the co-author, upon their request.
- Link to v2: https://lore.kernel.org/r/20250204-exynos7870-pmu-clocks-v1-0-a3030ae5bb53@disroot.org
Changes in v2:
- Drop all patches from v1 except:
- dt-bindings: clock: add clock definitions for exynos7870 CMU
- dt-bindings: clock: document exynos7870 clock driver CMU bindings
- Add patch for adding appropriate PMU compatible.
- Add patches for CMU and CLKOUT drivers.
- Link to v1: https://lore.kernel.org/all/20250203-exynos7870-v1-0-2b6df476a3f0@disroot.org/
---
Kaustabh Chakraborty (5):
dt-bindings: clock: add clock definitions for exynos7870 CMU
dt-bindings: clock: document exynos7870 clock driver CMU bindings
dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible
clk: samsung: add initial exynos7870 clock driver
clk: samsung: add exynos7870 CLKOUT support
.../bindings/clock/samsung,exynos7870-clock.yaml | 227 +++
.../bindings/soc/samsung/exynos-pmu.yaml | 1 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos-clkout.c | 3 +
drivers/clk/samsung/clk-exynos7870.c | 1830 ++++++++++++++++++++
include/dt-bindings/clock/exynos7870.h | 324 ++++
6 files changed, 2386 insertions(+)
---
base-commit: e5d3fd687aac5eceb1721fa92b9f49afcf4c3717
change-id: 20250203-exynos7870-pmu-clocks-d0b330970ea7
Best regards,
--
Kaustabh Chakraborty <kauschluss@disroot.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-18 18:50 [PATCH v3 0/5] Introduce support for Exynos7870 clocks and PMU Kaustabh Chakraborty
@ 2025-02-18 18:50 ` Kaustabh Chakraborty
2025-02-19 8:07 ` Krzysztof Kozlowski
2025-02-23 9:57 ` Krzysztof Kozlowski
2025-02-18 18:50 ` [PATCH v3 2/5] dt-bindings: clock: document exynos7870 clock driver CMU bindings Kaustabh Chakraborty
` (3 subsequent siblings)
4 siblings, 2 replies; 18+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-18 18:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, Kaustabh Chakraborty
Add unique identifiers for exynos7870 clocks for every bank. It adds all
clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
CMU_PERI.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++++++++++
1 file changed, 324 insertions(+)
diff --git a/include/dt-bindings/clock/exynos7870.h b/include/dt-bindings/clock/exynos7870.h
new file mode 100644
index 0000000000000000000000000000000000000000..57d04bbe342d835abbba34df542671dbdea427b5
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7870.h
@@ -0,0 +1,324 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Kaustabh Chakraborty <kauschluss@disroot.org>
+ *
+ * Device Tree binding constants for Exynos7870 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7870_H
+
+/* CMU_MIF */
+#define CLK_DOUT_MIF_APB 1
+#define CLK_DOUT_MIF_BUSD 2
+#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3
+#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4
+#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5
+#define CLK_DOUT_MIF_CMU_FSYS_BUS 6
+#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7
+#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8
+#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9
+#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10
+#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11
+#define CLK_DOUT_MIF_CMU_ISP_CAM 12
+#define CLK_DOUT_MIF_CMU_ISP_ISP 13
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16
+#define CLK_DOUT_MIF_CMU_ISP_VRA 17
+#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18
+#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19
+#define CLK_DOUT_MIF_CMU_PERI_BUS 20
+#define CLK_DOUT_MIF_CMU_PERI_SPI0 21
+#define CLK_DOUT_MIF_CMU_PERI_SPI1 22
+#define CLK_DOUT_MIF_CMU_PERI_SPI2 23
+#define CLK_DOUT_MIF_CMU_PERI_SPI3 24
+#define CLK_DOUT_MIF_CMU_PERI_SPI4 25
+#define CLK_DOUT_MIF_CMU_PERI_UART0 26
+#define CLK_DOUT_MIF_CMU_PERI_UART1 27
+#define CLK_DOUT_MIF_CMU_PERI_UART2 28
+#define CLK_DOUT_MIF_HSI2C 29
+#define CLK_FOUT_MIF_BUS_PLL 30
+#define CLK_FOUT_MIF_MEDIA_PLL 31
+#define CLK_FOUT_MIF_MEM_PLL 32
+#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33
+#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34
+#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35
+#define CLK_GOUT_MIF_CMU_FSYS_BUS 36
+#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37
+#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38
+#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39
+#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40
+#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41
+#define CLK_GOUT_MIF_CMU_ISP_CAM 42
+#define CLK_GOUT_MIF_CMU_ISP_ISP 43
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46
+#define CLK_GOUT_MIF_CMU_ISP_VRA 47
+#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48
+#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49
+#define CLK_GOUT_MIF_CMU_PERI_BUS 50
+#define CLK_GOUT_MIF_CMU_PERI_SPI0 51
+#define CLK_GOUT_MIF_CMU_PERI_SPI1 52
+#define CLK_GOUT_MIF_CMU_PERI_SPI2 53
+#define CLK_GOUT_MIF_CMU_PERI_SPI3 54
+#define CLK_GOUT_MIF_CMU_PERI_SPI4 55
+#define CLK_GOUT_MIF_CMU_PERI_UART0 56
+#define CLK_GOUT_MIF_CMU_PERI_UART1 57
+#define CLK_GOUT_MIF_CMU_PERI_UART2 58
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61
+#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62
+#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63
+#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64
+#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65
+#define CLK_GOUT_MIF_HSI2C_IPCLK 66
+#define CLK_GOUT_MIF_HSI2C_ITCLK 67
+#define CLK_GOUT_MIF_MUX_BUSD 68
+#define CLK_GOUT_MIF_MUX_BUS_PLL 69
+#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78
+#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79
+#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83
+#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84
+#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85
+#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86
+#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95
+#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96
+#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97
+#define CLK_GOUT_MIF_MUX_MEM_PLL 98
+#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99
+#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100
+#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101
+#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102
+#define CLK_MOUT_MIF_BUSD 103
+#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104
+#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105
+#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106
+#define CLK_MOUT_MIF_CMU_FSYS_BUS 107
+#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108
+#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109
+#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110
+#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111
+#define CLK_MOUT_MIF_CMU_ISP_CAM 112
+#define CLK_MOUT_MIF_CMU_ISP_ISP 113
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116
+#define CLK_MOUT_MIF_CMU_ISP_VRA 117
+#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118
+#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119
+#define CLK_MOUT_MIF_CMU_PERI_BUS 120
+#define CLK_MOUT_MIF_CMU_PERI_SPI0 121
+#define CLK_MOUT_MIF_CMU_PERI_SPI1 122
+#define CLK_MOUT_MIF_CMU_PERI_SPI2 123
+#define CLK_MOUT_MIF_CMU_PERI_SPI3 124
+#define CLK_MOUT_MIF_CMU_PERI_SPI4 125
+#define CLK_MOUT_MIF_CMU_PERI_UART0 126
+#define CLK_MOUT_MIF_CMU_PERI_UART1 127
+#define CLK_MOUT_MIF_CMU_PERI_UART2 128
+#define MIF_NR_CLK 129
+
+/* CMU_DISPAUD */
+#define CLK_DOUT_DISPAUD_APB 1
+#define CLK_DOUT_DISPAUD_DECON_ECLK 2
+#define CLK_DOUT_DISPAUD_DECON_VCLK 3
+#define CLK_DOUT_DISPAUD_MI2S 4
+#define CLK_DOUT_DISPAUD_MIXER 5
+#define CLK_FOUT_DISPAUD_AUD_PLL 6
+#define CLK_FOUT_DISPAUD_PLL 7
+#define CLK_GOUT_DISPAUD_APB_AUD 8
+#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9
+#define CLK_GOUT_DISPAUD_APB_DISP 10
+#define CLK_GOUT_DISPAUD_BUS 11
+#define CLK_GOUT_DISPAUD_BUS_DISP 12
+#define CLK_GOUT_DISPAUD_BUS_PPMU 13
+#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14
+#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15
+#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16
+#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17
+#define CLK_GOUT_DISPAUD_DECON_ECLK 18
+#define CLK_GOUT_DISPAUD_DECON_VCLK 19
+#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20
+#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21
+#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22
+#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23
+#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24
+#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25
+#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26
+#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27
+#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28
+#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29
+#define CLK_GOUT_DISPAUD_MUX_MI2S 30
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34
+#define CLK_GOUT_DISPAUD_MUX_PLL 35
+#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36
+#define CLK_MOUT_DISPAUD_BUS_USER 37
+#define CLK_MOUT_DISPAUD_DECON_ECLK 38
+#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39
+#define CLK_MOUT_DISPAUD_DECON_VCLK 40
+#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41
+#define CLK_MOUT_DISPAUD_MI2S 42
+#define DISPAUD_NR_CLK 43
+
+/* CMU_FSYS */
+#define CLK_FOUT_FSYS_USB_PLL 1
+#define CLK_GOUT_FSYS_BUSP3_HCLK 2
+#define CLK_GOUT_FSYS_MMC0_ACLK 3
+#define CLK_GOUT_FSYS_MMC1_ACLK 4
+#define CLK_GOUT_FSYS_MMC2_ACLK 5
+#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6
+#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7
+#define CLK_GOUT_FSYS_MUX_USB_PLL 8
+#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9
+#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10
+#define CLK_GOUT_FSYS_PPMU_ACLK 11
+#define CLK_GOUT_FSYS_PPMU_PCLK 12
+#define CLK_GOUT_FSYS_SROMC_HCLK 13
+#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14
+#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15
+#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16
+#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17
+#define FSYS_NR_CLK 18
+
+/* CMU_G3D */
+#define CLK_DOUT_G3D_APB 1
+#define CLK_DOUT_G3D_BUS 2
+#define CLK_FOUT_G3D_PLL 3
+#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4
+#define CLK_GOUT_G3D_ASYNC_PCLKM 5
+#define CLK_GOUT_G3D_CLK 6
+#define CLK_GOUT_G3D_MUX 7
+#define CLK_GOUT_G3D_MUX_PLL 8
+#define CLK_GOUT_G3D_MUX_PLL_CON 9
+#define CLK_GOUT_G3D_MUX_SWITCH_USER 10
+#define CLK_GOUT_G3D_PPMU_ACLK 11
+#define CLK_GOUT_G3D_PPMU_PCLK 12
+#define CLK_GOUT_G3D_QE_ACLK 13
+#define CLK_GOUT_G3D_QE_PCLK 14
+#define CLK_GOUT_G3D_SYSREG_PCLK 15
+#define CLK_MOUT_G3D 16
+#define CLK_MOUT_G3D_SWITCH_USER 17
+#define G3D_NR_CLK 18
+
+/* CMU_ISP */
+#define CLK_DOUT_ISP_APB 1
+#define CLK_DOUT_ISP_CAM_HALF 2
+#define CLK_FOUT_ISP_PLL 3
+#define CLK_GOUT_ISP_CAM 4
+#define CLK_GOUT_ISP_CAM_HALF 5
+#define CLK_GOUT_ISP_ISPD 6
+#define CLK_GOUT_ISP_ISPD_PPMU 7
+#define CLK_GOUT_ISP_MUX_CAM 8
+#define CLK_GOUT_ISP_MUX_CAM_USER 9
+#define CLK_GOUT_ISP_MUX_ISP 10
+#define CLK_GOUT_ISP_MUX_ISPD 11
+#define CLK_GOUT_ISP_MUX_PLL 12
+#define CLK_GOUT_ISP_MUX_PLL_CON 13
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17
+#define CLK_GOUT_ISP_MUX_USER 18
+#define CLK_GOUT_ISP_MUX_VRA 19
+#define CLK_GOUT_ISP_MUX_VRA_USER 20
+#define CLK_GOUT_ISP_VRA 21
+#define CLK_MOUT_ISP_CAM 22
+#define CLK_MOUT_ISP_CAM_USER 23
+#define CLK_MOUT_ISP_ISP 24
+#define CLK_MOUT_ISP_ISPD 25
+#define CLK_MOUT_ISP_USER 26
+#define CLK_MOUT_ISP_VRA 27
+#define CLK_MOUT_ISP_VRA_USER 28
+#define ISP_NR_CLK 29
+
+/* CMU_MFCMSCL */
+#define CLK_DOUT_MFCMSCL_APB 1
+#define CLK_GOUT_MFCMSCL_MFC 2
+#define CLK_GOUT_MFCMSCL_MSCL 3
+#define CLK_GOUT_MFCMSCL_MSCL_BI 4
+#define CLK_GOUT_MFCMSCL_MSCL_D 5
+#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6
+#define CLK_GOUT_MFCMSCL_MSCL_POLY 7
+#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8
+#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9
+#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10
+#define CLK_MOUT_MFCMSCL_MFC_USER 11
+#define CLK_MOUT_MFCMSCL_MSCL_USER 12
+#define MFCMSCL_NR_CLK 13
+
+/* CMU_PERI */
+#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1
+#define CLK_GOUT_PERI_GPIO2_PCLK 2
+#define CLK_GOUT_PERI_GPIO5_PCLK 3
+#define CLK_GOUT_PERI_GPIO6_PCLK 4
+#define CLK_GOUT_PERI_GPIO7_PCLK 5
+#define CLK_GOUT_PERI_HSI2C1_IPCLK 6
+#define CLK_GOUT_PERI_HSI2C2_IPCLK 7
+#define CLK_GOUT_PERI_HSI2C3_IPCLK 8
+#define CLK_GOUT_PERI_HSI2C4_IPCLK 9
+#define CLK_GOUT_PERI_HSI2C5_IPCLK 10
+#define CLK_GOUT_PERI_HSI2C6_IPCLK 11
+#define CLK_GOUT_PERI_I2C0_PCLK 12
+#define CLK_GOUT_PERI_I2C1_PCLK 13
+#define CLK_GOUT_PERI_I2C2_PCLK 14
+#define CLK_GOUT_PERI_I2C3_PCLK 15
+#define CLK_GOUT_PERI_I2C4_PCLK 16
+#define CLK_GOUT_PERI_I2C5_PCLK 17
+#define CLK_GOUT_PERI_I2C6_PCLK 18
+#define CLK_GOUT_PERI_I2C7_PCLK 19
+#define CLK_GOUT_PERI_I2C8_PCLK 20
+#define CLK_GOUT_PERI_MCT_PCLK 21
+#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22
+#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23
+#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24
+#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25
+#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26
+#define CLK_GOUT_PERI_SPI0_PCLK 27
+#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28
+#define CLK_GOUT_PERI_SPI1_PCLK 29
+#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30
+#define CLK_GOUT_PERI_SPI2_PCLK 31
+#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32
+#define CLK_GOUT_PERI_SPI3_PCLK 33
+#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34
+#define CLK_GOUT_PERI_SPI4_PCLK 35
+#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36
+#define CLK_GOUT_PERI_TMU_CLK 37
+#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38
+#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39
+#define CLK_GOUT_PERI_UART0_EXT_UCLK 40
+#define CLK_GOUT_PERI_UART0_PCLK 41
+#define CLK_GOUT_PERI_UART1_EXT_UCLK 42
+#define CLK_GOUT_PERI_UART1_PCLK 43
+#define CLK_GOUT_PERI_UART2_EXT_UCLK 44
+#define CLK_GOUT_PERI_UART2_PCLK 45
+#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46
+#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47
+#define PERI_NR_CLK 48
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 2/5] dt-bindings: clock: document exynos7870 clock driver CMU bindings
2025-02-18 18:50 [PATCH v3 0/5] Introduce support for Exynos7870 clocks and PMU Kaustabh Chakraborty
2025-02-18 18:50 ` [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU Kaustabh Chakraborty
@ 2025-02-18 18:50 ` Kaustabh Chakraborty
2025-02-19 8:05 ` Krzysztof Kozlowski
2025-02-18 18:50 ` [PATCH v3 3/5] dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible Kaustabh Chakraborty
` (2 subsequent siblings)
4 siblings, 1 reply; 18+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-18 18:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, Kaustabh Chakraborty
Provide dt-schema documentation for Exynos7870 SoC clock controller.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
.../bindings/clock/samsung,exynos7870-clock.yaml | 227 +++++++++++++++++++++
1 file changed, 227 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7870-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7870-clock.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..9361723f4f880de0b7127e6ab8f770990c9720e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7870-clock.yaml
@@ -0,0 +1,227 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos7870-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7870 SoC clock controller
+
+maintainers:
+ - Kaustabh Chakraborty <kauschluss@disroot.org>
+
+description: |
+ Exynos7870 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. The root clock in that root tree
+ is an external clock: OSCCLK (26 MHz). This external clock must be defined
+ as a fixed-rate clock in dts.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'dt-bindings/clock/exynos7870.h' header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos7870-cmu-mif
+ - samsung,exynos7870-cmu-dispaud
+ - samsung,exynos7870-cmu-fsys
+ - samsung,exynos7870-cmu-g3d
+ - samsung,exynos7870-cmu-isp
+ - samsung,exynos7870-cmu-mfcmscl
+ - samsung,exynos7870-cmu-peri
+
+ clocks:
+ minItems: 1
+ maxItems: 10
+
+ clock-names:
+ minItems: 1
+ maxItems: 10
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-mif
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-dispaud
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_DISPAUD bus clock (from CMU_MIF)
+ - description: DECON external clock (from CMU_MIF)
+ - description: DECON vertical clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: bus
+ - const: decon_eclk
+ - const: decon_vclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-fsys
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_FSYS bus clock (from CMU_MIF)
+ - description: USB20DRD clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: bus
+ - const: usb20drd_refclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-g3d
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: G3D switch clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: switch
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-isp
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: ISP camera clock (from CMU_MIF)
+ - description: ISP clock (from CMU_MIF)
+ - description: ISP VRA clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: cam
+ - const: isp
+ - const: vra
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-mfcmscl
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: MSCL clock (from CMU_MIF)
+ - description: MFC clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: mfc
+ - const: mscl
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-cmu-peri
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_PERI bus clock (from CMU_MIF)
+ - description: SPI0 clock (from CMU_MIF)
+ - description: SPI1 clock (from CMU_MIF)
+ - description: SPI2 clock (from CMU_MIF)
+ - description: SPI3 clock (from CMU_MIF)
+ - description: SPI4 clock (from CMU_MIF)
+ - description: UART0 clock (from CMU_MIF)
+ - description: UART1 clock (from CMU_MIF)
+ - description: UART2 clock (from CMU_MIF)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: bus
+ - const: spi0
+ - const: spi1
+ - const: spi2
+ - const: spi3
+ - const: spi4
+ - const: uart0
+ - const: uart1
+ - const: uart2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos7870.h>
+
+ cmu_peri: clock-controller@101f0000 {
+ compatible = "samsung,exynos7870-cmu-peri";
+ reg = <0x101f0000 0x1000>;
+ #clock-cells = <1>;
+
+ clock-names = "oscclk", "bus", "spi0", "spi1", "spi2",
+ "spi3", "spi4", "uart0", "uart1", "uart2";
+ clocks = <&oscclk>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>,
+ <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>;
+ };
+
+...
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 3/5] dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible
2025-02-18 18:50 [PATCH v3 0/5] Introduce support for Exynos7870 clocks and PMU Kaustabh Chakraborty
2025-02-18 18:50 ` [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU Kaustabh Chakraborty
2025-02-18 18:50 ` [PATCH v3 2/5] dt-bindings: clock: document exynos7870 clock driver CMU bindings Kaustabh Chakraborty
@ 2025-02-18 18:50 ` Kaustabh Chakraborty
2025-02-19 8:09 ` Krzysztof Kozlowski
2025-02-18 18:50 ` [PATCH v3 4/5] clk: samsung: add initial exynos7870 clock driver Kaustabh Chakraborty
2025-02-18 18:50 ` [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support Kaustabh Chakraborty
4 siblings, 1 reply; 18+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-18 18:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, Kaustabh Chakraborty
Document the compatible string for the Exynos7870 PMU. It's compatible
with the Exynos7 PMU design. It handles syscon reboot, syscon reboot mode,
as well as other system control registers (i.e registers for the USB PHY).
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
index 8e6d051d8c97de0c843a91350a5cb9c332b2d6ce..3baee81df54981cb4c6502c1ddf5be3d5e3184c3 100644
--- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
@@ -52,6 +52,7 @@ properties:
- const: syscon
- items:
- enum:
+ - samsung,exynos7870-pmu
- samsung,exynos7885-pmu
- samsung,exynos8895-pmu
- samsung,exynos9810-pmu
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 4/5] clk: samsung: add initial exynos7870 clock driver
2025-02-18 18:50 [PATCH v3 0/5] Introduce support for Exynos7870 clocks and PMU Kaustabh Chakraborty
` (2 preceding siblings ...)
2025-02-18 18:50 ` [PATCH v3 3/5] dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible Kaustabh Chakraborty
@ 2025-02-18 18:50 ` Kaustabh Chakraborty
2025-02-18 18:50 ` [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support Kaustabh Chakraborty
4 siblings, 0 replies; 18+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-18 18:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, Kaustabh Chakraborty
This is a basic implementation of the clock driver required by
Samsung's Exynos7870 SoC. It implements CMU_MIF, CMU_DISPAUD, CMU_FSYS,
CMU_G3D, CMU_ISP, CMU_MFCMSCL, and CMU_PERI. all other CMUs depend on
CMU_MIF.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos7870.c | 1830 ++++++++++++++++++++++++++++++++++
2 files changed, 1831 insertions(+)
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 90e5b114872c5057a9bd43fd1a16c2ad4630cc3f..9c8e4a293f1bdce4315082e157696d06cff3ffc5 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7870.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
diff --git a/drivers/clk/samsung/clk-exynos7870.c b/drivers/clk/samsung/clk-exynos7870.c
new file mode 100644
index 0000000000000000000000000000000000000000..9cbe4cde6068a8ae201e76997553774ba2a93f91
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7870.c
@@ -0,0 +1,1830 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Kaustabh Chakraborty <kauschluss@disroot.org>
+ *
+ * Common Clock Framework support for Exynos7870.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/exynos7870.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+
+/*
+ * Register offsets for CMU_MIF (0x10460000)
+ */
+#define PLL_LOCKTIME_MIF_MEM_PLL 0x0000
+#define PLL_LOCKTIME_MIF_MEDIA_PLL 0x0020
+#define PLL_LOCKTIME_MIF_BUS_PLL 0x0040
+#define PLL_CON0_MIF_MEM_PLL 0x0100
+#define PLL_CON0_MIF_MEDIA_PLL 0x0120
+#define PLL_CON0_MIF_BUS_PLL 0x0140
+#define CLK_CON_GAT_MIF_MUX_MEM_PLL 0x0200
+#define CLK_CON_GAT_MIF_MUX_MEM_PLL_CON 0x0200
+#define CLK_CON_GAT_MIF_MUX_MEDIA_PLL 0x0204
+#define CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON 0x0204
+#define CLK_CON_GAT_MIF_MUX_BUS_PLL 0x0208
+#define CLK_CON_GAT_MIF_MUX_BUS_PLL_CON 0x0208
+#define CLK_CON_GAT_MIF_MUX_BUSD 0x0220
+#define CLK_CON_MUX_MIF_BUSD 0x0220
+#define CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA 0x0264
+#define CLK_CON_MUX_MIF_CMU_ISP_VRA 0x0264
+#define CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM 0x0268
+#define CLK_CON_MUX_MIF_CMU_ISP_CAM 0x0268
+#define CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP 0x026c
+#define CLK_CON_MUX_MIF_CMU_ISP_ISP 0x026c
+#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS 0x0270
+#define CLK_CON_MUX_MIF_CMU_DISPAUD_BUS 0x0270
+#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 0x0274
+#define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK 0x0274
+#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 0x0278
+#define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK 0x0278
+#define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL 0x027c
+#define CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL 0x027c
+#define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC 0x0280
+#define CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC 0x0280
+#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS 0x0284
+#define CLK_CON_MUX_MIF_CMU_FSYS_BUS 0x0284
+#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0 0x0288
+#define CLK_CON_MUX_MIF_CMU_FSYS_MMC0 0x0288
+#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1 0x028c
+#define CLK_CON_MUX_MIF_CMU_FSYS_MMC1 0x028c
+#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2 0x0290
+#define CLK_CON_MUX_MIF_CMU_FSYS_MMC2 0x0290
+#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 0x029c
+#define CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK 0x029c
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS 0x02a0
+#define CLK_CON_MUX_MIF_CMU_PERI_BUS 0x02a0
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1 0x02a4
+#define CLK_CON_MUX_MIF_CMU_PERI_UART1 0x02a4
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2 0x02a8
+#define CLK_CON_MUX_MIF_CMU_PERI_UART2 0x02a8
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0 0x02ac
+#define CLK_CON_MUX_MIF_CMU_PERI_UART0 0x02ac
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2 0x02b0
+#define CLK_CON_MUX_MIF_CMU_PERI_SPI2 0x02b0
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1 0x02b4
+#define CLK_CON_MUX_MIF_CMU_PERI_SPI1 0x02b4
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0 0x02b8
+#define CLK_CON_MUX_MIF_CMU_PERI_SPI0 0x02b8
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3 0x02bc
+#define CLK_CON_MUX_MIF_CMU_PERI_SPI3 0x02bc
+#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4 0x02c0
+#define CLK_CON_MUX_MIF_CMU_PERI_SPI4 0x02c0
+#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0 0x02c4
+#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR0 0x02c4
+#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1 0x02c8
+#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR1 0x02c8
+#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2 0x02cc
+#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR2 0x02cc
+#define CLK_CON_DIV_MIF_BUSD 0x0420
+#define CLK_CON_DIV_MIF_APB 0x0424
+#define CLK_CON_DIV_MIF_HSI2C 0x0430
+#define CLK_CON_DIV_MIF_CMU_G3D_SWITCH 0x0460
+#define CLK_CON_DIV_MIF_CMU_ISP_VRA 0x0464
+#define CLK_CON_DIV_MIF_CMU_ISP_CAM 0x0468
+#define CLK_CON_DIV_MIF_CMU_ISP_ISP 0x046c
+#define CLK_CON_DIV_MIF_CMU_DISPAUD_BUS 0x0470
+#define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK 0x0474
+#define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK 0x0478
+#define CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL 0x047c
+#define CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC 0x0480
+#define CLK_CON_DIV_MIF_CMU_FSYS_BUS 0x0484
+#define CLK_CON_DIV_MIF_CMU_FSYS_MMC0 0x0488
+#define CLK_CON_DIV_MIF_CMU_FSYS_MMC1 0x048c
+#define CLK_CON_DIV_MIF_CMU_FSYS_MMC2 0x0490
+#define CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK 0x049c
+#define CLK_CON_DIV_MIF_CMU_PERI_BUS 0x04a0
+#define CLK_CON_DIV_MIF_CMU_PERI_UART1 0x04a4
+#define CLK_CON_DIV_MIF_CMU_PERI_UART2 0x04a8
+#define CLK_CON_DIV_MIF_CMU_PERI_UART0 0x04ac
+#define CLK_CON_DIV_MIF_CMU_PERI_SPI2 0x04b0
+#define CLK_CON_DIV_MIF_CMU_PERI_SPI1 0x04b4
+#define CLK_CON_DIV_MIF_CMU_PERI_SPI0 0x04b8
+#define CLK_CON_DIV_MIF_CMU_PERI_SPI3 0x04bc
+#define CLK_CON_DIV_MIF_CMU_PERI_SPI4 0x04c0
+#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR0 0x04c4
+#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR1 0x04c8
+#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR2 0x04cc
+#define CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS 0x080c
+#define CLK_CON_GAT_MIF_HSI2C_AP_PCLKS 0x0828
+#define CLK_CON_GAT_MIF_HSI2C_CP_PCLKS 0x0828
+#define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0 0x0828
+#define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1 0x0828
+#define CLK_CON_GAT_MIF_HSI2C_AP_PCLKM 0x0840
+#define CLK_CON_GAT_MIF_HSI2C_CP_PCLKM 0x0840
+#define CLK_CON_GAT_MIF_HSI2C_IPCLK 0x0840
+#define CLK_CON_GAT_MIF_HSI2C_ITCLK 0x0840
+#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C 0x0840
+#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0 0x0840
+#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1 0x0840
+#define CLK_CON_GAT_MIF_CMU_G3D_SWITCH 0x0860
+#define CLK_CON_GAT_MIF_CMU_ISP_VRA 0x0864
+#define CLK_CON_GAT_MIF_CMU_ISP_CAM 0x0868
+#define CLK_CON_GAT_MIF_CMU_ISP_ISP 0x086c
+#define CLK_CON_GAT_MIF_CMU_DISPAUD_BUS 0x0870
+#define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK 0x0874
+#define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK 0x0878
+#define CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL 0x087c
+#define CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC 0x0880
+#define CLK_CON_GAT_MIF_CMU_FSYS_BUS 0x0884
+#define CLK_CON_GAT_MIF_CMU_FSYS_MMC0 0x0888
+#define CLK_CON_GAT_MIF_CMU_FSYS_MMC1 0x088c
+#define CLK_CON_GAT_MIF_CMU_FSYS_MMC2 0x0890
+#define CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK 0x089c
+#define CLK_CON_GAT_MIF_CMU_PERI_BUS 0x08a0
+#define CLK_CON_GAT_MIF_CMU_PERI_UART1 0x08a4
+#define CLK_CON_GAT_MIF_CMU_PERI_UART2 0x08a8
+#define CLK_CON_GAT_MIF_CMU_PERI_UART0 0x08ac
+#define CLK_CON_GAT_MIF_CMU_PERI_SPI2 0x08b0
+#define CLK_CON_GAT_MIF_CMU_PERI_SPI1 0x08b4
+#define CLK_CON_GAT_MIF_CMU_PERI_SPI0 0x08b8
+#define CLK_CON_GAT_MIF_CMU_PERI_SPI3 0x08bc
+#define CLK_CON_GAT_MIF_CMU_PERI_SPI4 0x08c0
+#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR0 0x08c4
+#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR1 0x08c8
+#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR2 0x08cc
+
+static const unsigned long mif_clk_regs[] __initconst = {
+ PLL_LOCKTIME_MIF_MEM_PLL,
+ PLL_LOCKTIME_MIF_MEDIA_PLL,
+ PLL_LOCKTIME_MIF_BUS_PLL,
+ PLL_CON0_MIF_MEM_PLL,
+ PLL_CON0_MIF_MEDIA_PLL,
+ PLL_CON0_MIF_BUS_PLL,
+ CLK_CON_GAT_MIF_MUX_MEM_PLL,
+ CLK_CON_GAT_MIF_MUX_MEM_PLL_CON,
+ CLK_CON_GAT_MIF_MUX_MEDIA_PLL,
+ CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON,
+ CLK_CON_GAT_MIF_MUX_BUS_PLL,
+ CLK_CON_GAT_MIF_MUX_BUS_PLL_CON,
+ CLK_CON_GAT_MIF_MUX_BUSD,
+ CLK_CON_MUX_MIF_BUSD,
+ CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA,
+ CLK_CON_MUX_MIF_CMU_ISP_VRA,
+ CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM,
+ CLK_CON_MUX_MIF_CMU_ISP_CAM,
+ CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP,
+ CLK_CON_MUX_MIF_CMU_ISP_ISP,
+ CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS,
+ CLK_CON_MUX_MIF_CMU_DISPAUD_BUS,
+ CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK,
+ CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK,
+ CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK,
+ CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK,
+ CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL,
+ CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL,
+ CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC,
+ CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC,
+ CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS,
+ CLK_CON_MUX_MIF_CMU_FSYS_BUS,
+ CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0,
+ CLK_CON_MUX_MIF_CMU_FSYS_MMC0,
+ CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1,
+ CLK_CON_MUX_MIF_CMU_FSYS_MMC1,
+ CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2,
+ CLK_CON_MUX_MIF_CMU_FSYS_MMC2,
+ CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK,
+ CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS,
+ CLK_CON_MUX_MIF_CMU_PERI_BUS,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1,
+ CLK_CON_MUX_MIF_CMU_PERI_UART1,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2,
+ CLK_CON_MUX_MIF_CMU_PERI_UART2,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0,
+ CLK_CON_MUX_MIF_CMU_PERI_UART0,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2,
+ CLK_CON_MUX_MIF_CMU_PERI_SPI2,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1,
+ CLK_CON_MUX_MIF_CMU_PERI_SPI1,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0,
+ CLK_CON_MUX_MIF_CMU_PERI_SPI0,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3,
+ CLK_CON_MUX_MIF_CMU_PERI_SPI3,
+ CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4,
+ CLK_CON_MUX_MIF_CMU_PERI_SPI4,
+ CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0,
+ CLK_CON_MUX_MIF_CMU_ISP_SENSOR0,
+ CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1,
+ CLK_CON_MUX_MIF_CMU_ISP_SENSOR1,
+ CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2,
+ CLK_CON_MUX_MIF_CMU_ISP_SENSOR2,
+ CLK_CON_DIV_MIF_BUSD,
+ CLK_CON_DIV_MIF_APB,
+ CLK_CON_DIV_MIF_HSI2C,
+ CLK_CON_DIV_MIF_CMU_G3D_SWITCH,
+ CLK_CON_DIV_MIF_CMU_ISP_VRA,
+ CLK_CON_DIV_MIF_CMU_ISP_CAM,
+ CLK_CON_DIV_MIF_CMU_ISP_ISP,
+ CLK_CON_DIV_MIF_CMU_DISPAUD_BUS,
+ CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK,
+ CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK,
+ CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL,
+ CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC,
+ CLK_CON_DIV_MIF_CMU_FSYS_BUS,
+ CLK_CON_DIV_MIF_CMU_FSYS_MMC0,
+ CLK_CON_DIV_MIF_CMU_FSYS_MMC1,
+ CLK_CON_DIV_MIF_CMU_FSYS_MMC2,
+ CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK,
+ CLK_CON_DIV_MIF_CMU_PERI_BUS,
+ CLK_CON_DIV_MIF_CMU_PERI_UART1,
+ CLK_CON_DIV_MIF_CMU_PERI_UART2,
+ CLK_CON_DIV_MIF_CMU_PERI_UART0,
+ CLK_CON_DIV_MIF_CMU_PERI_SPI2,
+ CLK_CON_DIV_MIF_CMU_PERI_SPI1,
+ CLK_CON_DIV_MIF_CMU_PERI_SPI0,
+ CLK_CON_DIV_MIF_CMU_PERI_SPI3,
+ CLK_CON_DIV_MIF_CMU_PERI_SPI4,
+ CLK_CON_DIV_MIF_CMU_ISP_SENSOR0,
+ CLK_CON_DIV_MIF_CMU_ISP_SENSOR1,
+ CLK_CON_DIV_MIF_CMU_ISP_SENSOR2,
+ CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS,
+ CLK_CON_GAT_MIF_HSI2C_AP_PCLKS,
+ CLK_CON_GAT_MIF_HSI2C_CP_PCLKS,
+ CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0,
+ CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1,
+ CLK_CON_GAT_MIF_HSI2C_AP_PCLKM,
+ CLK_CON_GAT_MIF_HSI2C_CP_PCLKM,
+ CLK_CON_GAT_MIF_HSI2C_IPCLK,
+ CLK_CON_GAT_MIF_HSI2C_ITCLK,
+ CLK_CON_GAT_MIF_CP_PCLK_HSI2C,
+ CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0,
+ CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1,
+ CLK_CON_GAT_MIF_CMU_G3D_SWITCH,
+ CLK_CON_GAT_MIF_CMU_ISP_VRA,
+ CLK_CON_GAT_MIF_CMU_ISP_CAM,
+ CLK_CON_GAT_MIF_CMU_ISP_ISP,
+ CLK_CON_GAT_MIF_CMU_DISPAUD_BUS,
+ CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK,
+ CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK,
+ CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL,
+ CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC,
+ CLK_CON_GAT_MIF_CMU_FSYS_BUS,
+ CLK_CON_GAT_MIF_CMU_FSYS_MMC0,
+ CLK_CON_GAT_MIF_CMU_FSYS_MMC1,
+ CLK_CON_GAT_MIF_CMU_FSYS_MMC2,
+ CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK,
+ CLK_CON_GAT_MIF_CMU_PERI_BUS,
+ CLK_CON_GAT_MIF_CMU_PERI_UART1,
+ CLK_CON_GAT_MIF_CMU_PERI_UART2,
+ CLK_CON_GAT_MIF_CMU_PERI_UART0,
+ CLK_CON_GAT_MIF_CMU_PERI_SPI2,
+ CLK_CON_GAT_MIF_CMU_PERI_SPI1,
+ CLK_CON_GAT_MIF_CMU_PERI_SPI0,
+ CLK_CON_GAT_MIF_CMU_PERI_SPI3,
+ CLK_CON_GAT_MIF_CMU_PERI_SPI4,
+ CLK_CON_GAT_MIF_CMU_ISP_SENSOR0,
+ CLK_CON_GAT_MIF_CMU_ISP_SENSOR1,
+ CLK_CON_GAT_MIF_CMU_ISP_SENSOR2,
+};
+
+static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "ffac_mif_mux_bus_pll_div2", "gout_mif_mux_bus_pll_con", 1, 2,
+ 0),
+ FFACTOR(0, "ffac_mif_mux_media_pll_div2", "gout_mif_mux_media_pll_con",
+ 1, 2, 0),
+ FFACTOR(0, "ffac_mif_mux_mem_pll_div2", "gout_mif_mux_mem_pll_con", 1, 2,
+ 0),
+};
+
+static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
+ PLL(pll_1417x, CLK_FOUT_MIF_BUS_PLL, "fout_mif_bus_pll", "oscclk",
+ PLL_LOCKTIME_MIF_BUS_PLL, PLL_CON0_MIF_BUS_PLL, NULL),
+ PLL(pll_1417x, CLK_FOUT_MIF_MEDIA_PLL, "fout_mif_media_pll", "oscclk",
+ PLL_LOCKTIME_MIF_MEDIA_PLL, PLL_CON0_MIF_MEDIA_PLL, NULL),
+ PLL(pll_1417x, CLK_FOUT_MIF_MEM_PLL, "fout_mif_mem_pll", "oscclk",
+ PLL_LOCKTIME_MIF_MEM_PLL, PLL_CON0_MIF_MEM_PLL, NULL),
+};
+
+/* List of parent clocks for muxes in CMU_MIF */
+PNAME(mout_mif_cmu_dispaud_bus_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_dispaud_decon_eclk_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_dispaud_decon_vclk_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_fsys_bus_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_fsys_mmc0_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_fsys_mmc1_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_fsys_mmc2_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_fsys_usb20drd_refclk_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_isp_cam_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_isp_isp_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_isp_sensor0_p) = { "ffac_mif_mux_bus_pll_div2",
+ "oscclk" };
+PNAME(mout_mif_cmu_isp_sensor1_p) = { "ffac_mif_mux_bus_pll_div2",
+ "oscclk" };
+PNAME(mout_mif_cmu_isp_sensor2_p) = { "ffac_mif_mux_bus_pll_div2",
+ "oscclk" };
+PNAME(mout_mif_cmu_isp_vra_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2",
+ "gout_mif_mux_bus_pll_con" };
+PNAME(mout_mif_cmu_mfcmscl_mfc_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2",
+ "gout_mif_mux_bus_pll_con" };
+PNAME(mout_mif_cmu_mfcmscl_mscl_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2",
+ "gout_mif_mux_bus_pll_con" };
+PNAME(mout_mif_cmu_peri_bus_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_peri_spi0_p) = { "ffac_mif_mux_bus_pll_div2",
+ "oscclk" };
+PNAME(mout_mif_cmu_peri_spi2_p) = { "ffac_mif_mux_bus_pll_div2",
+ "oscclk" };
+PNAME(mout_mif_cmu_peri_spi1_p) = { "ffac_mif_mux_bus_pll_div2",
+ "oscclk" };
+PNAME(mout_mif_cmu_peri_spi4_p) = { "ffac_mif_mux_bus_pll_div2",
+ "oscclk" };
+PNAME(mout_mif_cmu_peri_spi3_p) = { "ffac_mif_mux_bus_pll_div2",
+ "oscclk" };
+PNAME(mout_mif_cmu_peri_uart1_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_peri_uart2_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_cmu_peri_uart0_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2" };
+PNAME(mout_mif_busd_p) = { "ffac_mif_mux_bus_pll_div2",
+ "ffac_mif_mux_media_pll_div2",
+ "ffac_mif_mux_mem_pll_div2" };
+
+static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_MIF_CMU_DISPAUD_BUS, "mout_mif_cmu_dispaud_bus",
+ mout_mif_cmu_dispaud_bus_p, CLK_CON_MUX_MIF_CMU_DISPAUD_BUS, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK,
+ "mout_mif_cmu_dispaud_decon_eclk",
+ mout_mif_cmu_dispaud_decon_eclk_p,
+ CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK,
+ "mout_mif_cmu_dispaud_decon_vclk",
+ mout_mif_cmu_dispaud_decon_vclk_p,
+ CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_FSYS_BUS, "mout_mif_cmu_fsys_bus",
+ mout_mif_cmu_fsys_bus_p, CLK_CON_MUX_MIF_CMU_FSYS_BUS, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_FSYS_MMC0, "mout_mif_cmu_fsys_mmc0",
+ mout_mif_cmu_fsys_mmc0_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC0, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_FSYS_MMC1, "mout_mif_cmu_fsys_mmc1",
+ mout_mif_cmu_fsys_mmc1_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC1, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_FSYS_MMC2, "mout_mif_cmu_fsys_mmc2",
+ mout_mif_cmu_fsys_mmc2_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC2, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK,
+ "mout_mif_cmu_fsys_usb20drd_refclk",
+ mout_mif_cmu_fsys_usb20drd_refclk_p,
+ CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_ISP_CAM, "mout_mif_cmu_isp_cam",
+ mout_mif_cmu_isp_cam_p, CLK_CON_MUX_MIF_CMU_ISP_CAM, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_ISP_ISP, "mout_mif_cmu_isp_isp",
+ mout_mif_cmu_isp_isp_p, CLK_CON_MUX_MIF_CMU_ISP_ISP, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR0, "mout_mif_cmu_isp_sensor0",
+ mout_mif_cmu_isp_sensor0_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR0, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR1, "mout_mif_cmu_isp_sensor1",
+ mout_mif_cmu_isp_sensor1_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR1, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR2, "mout_mif_cmu_isp_sensor2",
+ mout_mif_cmu_isp_sensor2_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR2, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_ISP_VRA, "mout_mif_cmu_isp_vra",
+ mout_mif_cmu_isp_vra_p, CLK_CON_MUX_MIF_CMU_ISP_VRA, 12, 2),
+ MUX(CLK_MOUT_MIF_CMU_MFCMSCL_MFC, "mout_mif_cmu_mfcmscl_mfc",
+ mout_mif_cmu_mfcmscl_mfc_p, CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC, 12, 2),
+ MUX(CLK_MOUT_MIF_CMU_MFCMSCL_MSCL, "mout_mif_cmu_mfcmscl_mscl",
+ mout_mif_cmu_mfcmscl_mscl_p, CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL, 12,
+ 2),
+ MUX(CLK_MOUT_MIF_CMU_PERI_BUS, "mout_mif_cmu_peri_bus",
+ mout_mif_cmu_peri_bus_p, CLK_CON_MUX_MIF_CMU_PERI_BUS, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_PERI_SPI0, "mout_mif_cmu_peri_spi0",
+ mout_mif_cmu_peri_spi0_p, CLK_CON_MUX_MIF_CMU_PERI_SPI0, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_PERI_SPI2, "mout_mif_cmu_peri_spi2",
+ mout_mif_cmu_peri_spi2_p, CLK_CON_MUX_MIF_CMU_PERI_SPI2, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_PERI_SPI1, "mout_mif_cmu_peri_spi1",
+ mout_mif_cmu_peri_spi1_p, CLK_CON_MUX_MIF_CMU_PERI_SPI1, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_PERI_SPI4, "mout_mif_cmu_peri_spi4",
+ mout_mif_cmu_peri_spi4_p, CLK_CON_MUX_MIF_CMU_PERI_SPI4, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_PERI_SPI3, "mout_mif_cmu_peri_spi3",
+ mout_mif_cmu_peri_spi3_p, CLK_CON_MUX_MIF_CMU_PERI_SPI3, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_PERI_UART1, "mout_mif_cmu_peri_uart1",
+ mout_mif_cmu_peri_uart1_p, CLK_CON_MUX_MIF_CMU_PERI_UART1, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_PERI_UART2, "mout_mif_cmu_peri_uart2",
+ mout_mif_cmu_peri_uart2_p, CLK_CON_MUX_MIF_CMU_PERI_UART2, 12, 1),
+ MUX(CLK_MOUT_MIF_CMU_PERI_UART0, "mout_mif_cmu_peri_uart0",
+ mout_mif_cmu_peri_uart0_p, CLK_CON_MUX_MIF_CMU_PERI_UART0, 12, 1),
+ MUX(CLK_MOUT_MIF_BUSD, "mout_mif_busd", mout_mif_busd_p,
+ CLK_CON_MUX_MIF_BUSD, 12, 2),
+};
+
+static const struct samsung_div_clock mif_div_clks[] __initconst = {
+ DIV(CLK_DOUT_MIF_CMU_DISPAUD_BUS, "dout_mif_cmu_dispaud_bus",
+ "gout_mif_mux_cmu_dispaud_bus", CLK_CON_DIV_MIF_CMU_DISPAUD_BUS, 0,
+ 4),
+ DIV(CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK,
+ "dout_mif_cmu_dispaud_decon_eclk",
+ "gout_mif_mux_cmu_dispaud_decon_eclk",
+ CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK,
+ "dout_mif_cmu_dispaud_decon_vclk",
+ "gout_mif_mux_cmu_dispaud_decon_vclk",
+ CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_FSYS_BUS, "dout_mif_cmu_fsys_bus",
+ "gout_mif_mux_cmu_fsys_bus", CLK_CON_DIV_MIF_CMU_FSYS_BUS, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_FSYS_MMC0, "dout_mif_cmu_fsys_mmc0",
+ "gout_mif_mux_cmu_fsys_mmc0", CLK_CON_DIV_MIF_CMU_FSYS_MMC0, 0, 10),
+ DIV(CLK_DOUT_MIF_CMU_FSYS_MMC1, "dout_mif_cmu_fsys_mmc1",
+ "gout_mif_mux_cmu_fsys_mmc1", CLK_CON_DIV_MIF_CMU_FSYS_MMC1, 0, 10),
+ DIV(CLK_DOUT_MIF_CMU_FSYS_MMC2, "dout_mif_cmu_fsys_mmc2",
+ "gout_mif_mux_cmu_fsys_mmc2", CLK_CON_DIV_MIF_CMU_FSYS_MMC2, 0, 10),
+ DIV(CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK,
+ "dout_mif_cmu_fsys_usb20drd_refclk",
+ "gout_mif_mux_cmu_fsys_usb20drd_refclk",
+ CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_G3D_SWITCH, "dout_mif_cmu_g3d_switch",
+ "ffac_mif_mux_bus_pll_div2", CLK_CON_DIV_MIF_CMU_G3D_SWITCH, 0, 2),
+ DIV(CLK_DOUT_MIF_CMU_ISP_CAM, "dout_mif_cmu_isp_cam",
+ "gout_mif_mux_cmu_isp_cam", CLK_CON_DIV_MIF_CMU_ISP_CAM, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_ISP_ISP, "dout_mif_cmu_isp_isp",
+ "gout_mif_mux_cmu_isp_isp", CLK_CON_DIV_MIF_CMU_ISP_ISP, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR0, "dout_mif_cmu_isp_sensor0",
+ "gout_mif_mux_cmu_isp_sensor0", CLK_CON_DIV_MIF_CMU_ISP_SENSOR0, 0,
+ 6),
+ DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR1, "dout_mif_cmu_isp_sensor1",
+ "gout_mif_mux_cmu_isp_sensor1", CLK_CON_DIV_MIF_CMU_ISP_SENSOR1, 0,
+ 6),
+ DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR2, "dout_mif_cmu_isp_sensor2",
+ "gout_mif_mux_cmu_isp_sensor2", CLK_CON_DIV_MIF_CMU_ISP_SENSOR2, 0,
+ 6),
+ DIV(CLK_DOUT_MIF_CMU_ISP_VRA, "dout_mif_cmu_isp_vra",
+ "gout_mif_mux_cmu_isp_vra", CLK_CON_DIV_MIF_CMU_ISP_VRA, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_MFCMSCL_MFC, "dout_mif_cmu_mfcmscl_mfc",
+ "gout_mif_mux_cmu_mfcmscl_mfc", CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC, 0,
+ 4),
+ DIV(CLK_DOUT_MIF_CMU_MFCMSCL_MSCL, "dout_mif_cmu_mfcmscl_mscl",
+ "gout_mif_mux_cmu_mfcmscl_mscl", CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL,
+ 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_PERI_BUS, "dout_mif_cmu_peri_bus",
+ "gout_mif_mux_cmu_peri_bus", CLK_CON_DIV_MIF_CMU_PERI_BUS, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_PERI_SPI0, "dout_mif_cmu_peri_spi0",
+ "gout_mif_mux_cmu_peri_spi0", CLK_CON_DIV_MIF_CMU_PERI_SPI0, 0, 6),
+ DIV(CLK_DOUT_MIF_CMU_PERI_SPI2, "dout_mif_cmu_peri_spi2",
+ "gout_mif_mux_cmu_peri_spi2", CLK_CON_DIV_MIF_CMU_PERI_SPI2, 0, 6),
+ DIV(CLK_DOUT_MIF_CMU_PERI_SPI1, "dout_mif_cmu_peri_spi1",
+ "gout_mif_mux_cmu_peri_spi1", CLK_CON_DIV_MIF_CMU_PERI_SPI1, 0, 6),
+ DIV(CLK_DOUT_MIF_CMU_PERI_SPI4, "dout_mif_cmu_peri_spi4",
+ "gout_mif_mux_cmu_peri_spi4", CLK_CON_DIV_MIF_CMU_PERI_SPI4, 0, 6),
+ DIV(CLK_DOUT_MIF_CMU_PERI_SPI3, "dout_mif_cmu_peri_spi3",
+ "gout_mif_mux_cmu_peri_spi3", CLK_CON_DIV_MIF_CMU_PERI_SPI3, 0, 6),
+ DIV(CLK_DOUT_MIF_CMU_PERI_UART1, "dout_mif_cmu_peri_uart1",
+ "gout_mif_mux_cmu_peri_uart1", CLK_CON_DIV_MIF_CMU_PERI_UART1, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_PERI_UART2, "dout_mif_cmu_peri_uart2",
+ "gout_mif_mux_cmu_peri_uart2", CLK_CON_DIV_MIF_CMU_PERI_UART2, 0, 4),
+ DIV(CLK_DOUT_MIF_CMU_PERI_UART0, "dout_mif_cmu_peri_uart0",
+ "gout_mif_mux_cmu_peri_uart0", CLK_CON_DIV_MIF_CMU_PERI_UART0, 0, 4),
+ DIV(CLK_DOUT_MIF_APB, "dout_mif_apb", "dout_mif_busd",
+ CLK_CON_DIV_MIF_APB, 0, 2),
+ DIV(CLK_DOUT_MIF_BUSD, "dout_mif_busd", "gout_mif_mux_busd",
+ CLK_CON_DIV_MIF_BUSD, 0, 4),
+ DIV(CLK_DOUT_MIF_HSI2C, "dout_mif_hsi2c", "ffac_mif_mux_media_pll_div2",
+ CLK_CON_DIV_MIF_HSI2C, 0, 4),
+};
+
+static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_MIF_CMU_DISPAUD_BUS, "gout_mif_cmu_dispaud_bus",
+ "dout_mif_cmu_dispaud_bus", CLK_CON_GAT_MIF_CMU_DISPAUD_BUS, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK,
+ "gout_mif_cmu_dispaud_decon_eclk",
+ "dout_mif_cmu_dispaud_decon_eclk",
+ CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK,
+ "gout_mif_cmu_dispaud_decon_vclk",
+ "dout_mif_cmu_dispaud_decon_vclk",
+ CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_FSYS_BUS, "gout_mif_cmu_fsys_bus",
+ "dout_mif_cmu_fsys_bus", CLK_CON_GAT_MIF_CMU_FSYS_BUS, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_FSYS_MMC0, "gout_mif_cmu_fsys_mmc0",
+ "dout_mif_cmu_fsys_mmc0", CLK_CON_GAT_MIF_CMU_FSYS_MMC0, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_FSYS_MMC1, "gout_mif_cmu_fsys_mmc1",
+ "dout_mif_cmu_fsys_mmc1", CLK_CON_GAT_MIF_CMU_FSYS_MMC1, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_FSYS_MMC2, "gout_mif_cmu_fsys_mmc2",
+ "dout_mif_cmu_fsys_mmc2", CLK_CON_GAT_MIF_CMU_FSYS_MMC2, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK,
+ "gout_mif_cmu_fsys_usb20drd_refclk",
+ "dout_mif_cmu_fsys_usb20drd_refclk",
+ CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK, 0, CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_MIF_CMU_G3D_SWITCH, "gout_mif_cmu_g3d_switch",
+ "dout_mif_cmu_g3d_switch", CLK_CON_GAT_MIF_CMU_G3D_SWITCH, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_ISP_CAM, "gout_mif_cmu_isp_cam",
+ "dout_mif_cmu_isp_cam", CLK_CON_GAT_MIF_CMU_ISP_CAM, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_ISP_ISP, "gout_mif_cmu_isp_isp",
+ "dout_mif_cmu_isp_isp", CLK_CON_GAT_MIF_CMU_ISP_ISP, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR0, "gout_mif_cmu_isp_sensor0",
+ "dout_mif_cmu_isp_sensor0", CLK_CON_GAT_MIF_CMU_ISP_SENSOR0, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR1, "gout_mif_cmu_isp_sensor1",
+ "dout_mif_cmu_isp_sensor1", CLK_CON_GAT_MIF_CMU_ISP_SENSOR1, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR2, "gout_mif_cmu_isp_sensor2",
+ "dout_mif_cmu_isp_sensor2", CLK_CON_GAT_MIF_CMU_ISP_SENSOR2, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_ISP_VRA, "gout_mif_cmu_isp_vra",
+ "dout_mif_cmu_isp_vra", CLK_CON_GAT_MIF_CMU_ISP_VRA, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_MFCMSCL_MFC, "gout_mif_cmu_mfcmscl_mfc",
+ "dout_mif_cmu_mfcmscl_mfc", CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_MFCMSCL_MSCL, "gout_mif_cmu_mfcmscl_mscl",
+ "dout_mif_cmu_mfcmscl_mscl", CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_BUS, "gout_mif_cmu_peri_bus",
+ "dout_mif_cmu_peri_bus", CLK_CON_GAT_MIF_CMU_PERI_BUS, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_SPI0, "gout_mif_cmu_peri_spi0",
+ "dout_mif_cmu_peri_spi0", CLK_CON_GAT_MIF_CMU_PERI_SPI0, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_SPI2, "gout_mif_cmu_peri_spi2",
+ "dout_mif_cmu_peri_spi2", CLK_CON_GAT_MIF_CMU_PERI_SPI2, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_SPI1, "gout_mif_cmu_peri_spi1",
+ "dout_mif_cmu_peri_spi1", CLK_CON_GAT_MIF_CMU_PERI_SPI1, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_SPI4, "gout_mif_cmu_peri_spi4",
+ "dout_mif_cmu_peri_spi4", CLK_CON_GAT_MIF_CMU_PERI_SPI4, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_SPI3, "gout_mif_cmu_peri_spi3",
+ "dout_mif_cmu_peri_spi3", CLK_CON_GAT_MIF_CMU_PERI_SPI3, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_UART1, "gout_mif_cmu_peri_uart1",
+ "dout_mif_cmu_peri_uart1", CLK_CON_GAT_MIF_CMU_PERI_UART1, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_UART2, "gout_mif_cmu_peri_uart2",
+ "dout_mif_cmu_peri_uart2", CLK_CON_GAT_MIF_CMU_PERI_UART2, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CMU_PERI_UART0, "gout_mif_cmu_peri_uart0",
+ "dout_mif_cmu_peri_uart0", CLK_CON_GAT_MIF_CMU_PERI_UART0, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_HSI2C_AP_PCLKM, "gout_mif_hsi2c_ap_pclkm",
+ "dout_mif_hsi2c", CLK_CON_GAT_MIF_HSI2C_AP_PCLKM, 0,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_HSI2C_AP_PCLKS, "gout_mif_hsi2c_ap_pclks",
+ "dout_mif_apb", CLK_CON_GAT_MIF_HSI2C_AP_PCLKS, 14, CLK_IS_CRITICAL
+ | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_HSI2C_CP_PCLKM, "gout_mif_hsi2c_cp_pclkm",
+ "dout_mif_hsi2c", CLK_CON_GAT_MIF_HSI2C_CP_PCLKM, 1,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_HSI2C_CP_PCLKS, "gout_mif_hsi2c_cp_pclks",
+ "dout_mif_apb", CLK_CON_GAT_MIF_HSI2C_CP_PCLKS, 15, CLK_IS_CRITICAL
+ | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_HSI2C_IPCLK, "gout_mif_hsi2c_ipclk", "dout_mif_hsi2c",
+ CLK_CON_GAT_MIF_HSI2C_IPCLK, 2, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_HSI2C_ITCLK, "gout_mif_hsi2c_itclk", "dout_mif_hsi2c",
+ CLK_CON_GAT_MIF_HSI2C_ITCLK, 3, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C, "gout_mif_cp_pclk_hsi2c",
+ "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C, 6, CLK_IS_CRITICAL
+ | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0, "gout_mif_cp_pclk_hsi2c_bat_0",
+ "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0, 4,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1, "gout_mif_cp_pclk_hsi2c_bat_1",
+ "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1, 5,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS, "gout_mif_wrap_adc_if_osc_sys",
+ "oscclk", CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS, 3,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0, "gout_mif_wrap_adc_if_pclk_s0",
+ "dout_mif_apb", CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0, 20,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1, "gout_mif_wrap_adc_if_pclk_s1",
+ "dout_mif_apb", CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_BUS_PLL, "gout_mif_mux_bus_pll",
+ "gout_mif_mux_bus_pll_con", CLK_CON_GAT_MIF_MUX_BUS_PLL, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_BUS_PLL_CON, "gout_mif_mux_bus_pll_con",
+ "fout_mif_bus_pll", CLK_CON_GAT_MIF_MUX_BUS_PLL_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS, "gout_mif_mux_cmu_dispaud_bus",
+ "mout_mif_cmu_dispaud_bus", CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS,
+ 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK,
+ "gout_mif_mux_cmu_dispaud_decon_eclk",
+ "mout_mif_cmu_dispaud_decon_eclk",
+ CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK,
+ "gout_mif_mux_cmu_dispaud_decon_vclk",
+ "mout_mif_cmu_dispaud_decon_vclk",
+ CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_BUS, "gout_mif_mux_cmu_fsys_bus",
+ "mout_mif_cmu_fsys_bus", CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0, "gout_mif_mux_cmu_fsys_mmc0",
+ "mout_mif_cmu_fsys_mmc0", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1, "gout_mif_mux_cmu_fsys_mmc1",
+ "mout_mif_cmu_fsys_mmc1", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2, "gout_mif_mux_cmu_fsys_mmc2",
+ "mout_mif_cmu_fsys_mmc2", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK,
+ "gout_mif_mux_cmu_fsys_usb20drd_refclk",
+ "mout_mif_cmu_fsys_usb20drd_refclk",
+ CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_ISP_CAM, "gout_mif_mux_cmu_isp_cam",
+ "mout_mif_cmu_isp_cam", CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_ISP_ISP, "gout_mif_mux_cmu_isp_isp",
+ "mout_mif_cmu_isp_isp", CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0, "gout_mif_mux_cmu_isp_sensor0",
+ "mout_mif_cmu_isp_sensor0", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0,
+ 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1, "gout_mif_mux_cmu_isp_sensor1",
+ "mout_mif_cmu_isp_sensor1", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1,
+ 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2, "gout_mif_mux_cmu_isp_sensor2",
+ "mout_mif_cmu_isp_sensor2", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2,
+ 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_ISP_VRA, "gout_mif_mux_cmu_isp_vra",
+ "mout_mif_cmu_isp_vra", CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC, "gout_mif_mux_cmu_mfcmscl_mfc",
+ "mout_mif_cmu_mfcmscl_mfc", CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC,
+ 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL, "gout_mif_mux_cmu_mfcmscl_mscl",
+ "mout_mif_cmu_mfcmscl_mscl", CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL,
+ 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_BUS, "gout_mif_mux_cmu_peri_bus",
+ "mout_mif_cmu_peri_bus", CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI0, "gout_mif_mux_cmu_peri_spi0",
+ "mout_mif_cmu_peri_spi0", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI2, "gout_mif_mux_cmu_peri_spi2",
+ "mout_mif_cmu_peri_spi2", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI1, "gout_mif_mux_cmu_peri_spi1",
+ "mout_mif_cmu_peri_spi1", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI4, "gout_mif_mux_cmu_peri_spi4",
+ "mout_mif_cmu_peri_spi4", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI3, "gout_mif_mux_cmu_peri_spi3",
+ "mout_mif_cmu_peri_spi3", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART1, "gout_mif_mux_cmu_peri_uart1",
+ "mout_mif_cmu_peri_uart1", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART2, "gout_mif_mux_cmu_peri_uart2",
+ "mout_mif_cmu_peri_uart2", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART0, "gout_mif_mux_cmu_peri_uart0",
+ "mout_mif_cmu_peri_uart0", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_BUSD, "gout_mif_mux_busd", "mout_mif_busd",
+ CLK_CON_GAT_MIF_MUX_BUSD, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_MEDIA_PLL, "gout_mif_mux_media_pll",
+ "gout_mif_mux_media_pll_con", CLK_CON_GAT_MIF_MUX_MEDIA_PLL, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_MEDIA_PLL_CON, "gout_mif_mux_media_pll_con",
+ "fout_mif_media_pll", CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_MEM_PLL, "gout_mif_mux_mem_pll",
+ "gout_mif_mux_mem_pll_con", CLK_CON_GAT_MIF_MUX_MEM_PLL, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MIF_MUX_MEM_PLL_CON, "gout_mif_mux_mem_pll_con",
+ "fout_mif_mem_pll", CLK_CON_GAT_MIF_MUX_MEM_PLL_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info mif_cmu_info __initconst = {
+ .fixed_factor_clks = mif_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
+ .pll_clks = mif_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
+ .mux_clks = mif_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
+ .div_clks = mif_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mif_div_clks),
+ .gate_clks = mif_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
+ .clk_regs = mif_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
+ .nr_clk_ids = MIF_NR_CLK,
+};
+
+/*
+ * Register offsets for CMU_DISPAUD (0x148d0000)
+ */
+#define PLL_LOCKTIME_DISPAUD_PLL 0x0000
+#define PLL_LOCKTIME_DISPAUD_AUD_PLL 0x00c0
+#define PLL_CON0_DISPAUD_PLL 0x0100
+#define PLL_CON0_DISPAUD_AUD_PLL 0x01c0
+#define CLK_CON_GAT_DISPAUD_MUX_PLL 0x0200
+#define CLK_CON_GAT_DISPAUD_MUX_PLL_CON 0x0200
+#define CLK_CON_GAT_DISPAUD_MUX_AUD_PLL 0x0204
+#define CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON 0x0204
+#define CLK_CON_GAT_DISPAUD_MUX_BUS_USER 0x0210
+#define CLK_CON_MUX_DISPAUD_BUS_USER 0x0210
+#define CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER 0x0214
+#define CLK_CON_MUX_DISPAUD_DECON_VCLK_USER 0x0214
+#define CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER 0x0218
+#define CLK_CON_MUX_DISPAUD_DECON_ECLK_USER 0x0218
+#define CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK 0x021c
+#define CLK_CON_MUX_DISPAUD_DECON_VCLK 0x021c
+#define CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK 0x0220
+#define CLK_CON_MUX_DISPAUD_DECON_ECLK 0x0220
+#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 0x0224
+#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 0x0224
+#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 0x0228
+#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 0x0228
+#define CLK_CON_GAT_DISPAUD_MUX_MI2S 0x022c
+#define CLK_CON_MUX_DISPAUD_MI2S 0x022c
+#define CLK_CON_DIV_DISPAUD_APB 0x0400
+#define CLK_CON_DIV_DISPAUD_DECON_VCLK 0x0404
+#define CLK_CON_DIV_DISPAUD_DECON_ECLK 0x0408
+#define CLK_CON_DIV_DISPAUD_MI2S 0x040c
+#define CLK_CON_DIV_DISPAUD_MIXER 0x0410
+#define CLK_CON_GAT_DISPAUD_BUS 0x0810
+#define CLK_CON_GAT_DISPAUD_BUS_DISP 0x0810
+#define CLK_CON_GAT_DISPAUD_BUS_PPMU 0x0810
+#define CLK_CON_GAT_DISPAUD_APB_AUD 0x0814
+#define CLK_CON_GAT_DISPAUD_APB_AUD_AMP 0x0814
+#define CLK_CON_GAT_DISPAUD_APB_DISP 0x0814
+#define CLK_CON_GAT_DISPAUD_DECON_VCLK 0x081c
+#define CLK_CON_GAT_DISPAUD_DECON_ECLK 0x0820
+#define CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI 0x082c
+#define CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI 0x082c
+#define CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK 0x0830
+#define CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 0x0834
+#define CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 0x0838
+#define CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK 0x083c
+#define CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 0x0840
+
+static const unsigned long dispaud_clk_regs[] __initconst = {
+ PLL_LOCKTIME_DISPAUD_PLL,
+ PLL_LOCKTIME_DISPAUD_AUD_PLL,
+ PLL_CON0_DISPAUD_PLL,
+ PLL_CON0_DISPAUD_AUD_PLL,
+ CLK_CON_GAT_DISPAUD_MUX_PLL,
+ CLK_CON_GAT_DISPAUD_MUX_PLL_CON,
+ CLK_CON_GAT_DISPAUD_MUX_AUD_PLL,
+ CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON,
+ CLK_CON_GAT_DISPAUD_MUX_BUS_USER,
+ CLK_CON_MUX_DISPAUD_BUS_USER,
+ CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER,
+ CLK_CON_MUX_DISPAUD_DECON_VCLK_USER,
+ CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER,
+ CLK_CON_MUX_DISPAUD_DECON_ECLK_USER,
+ CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK,
+ CLK_CON_MUX_DISPAUD_DECON_VCLK,
+ CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK,
+ CLK_CON_MUX_DISPAUD_DECON_ECLK,
+ CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER,
+ CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON,
+ CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER,
+ CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON,
+ CLK_CON_GAT_DISPAUD_MUX_MI2S,
+ CLK_CON_MUX_DISPAUD_MI2S,
+ CLK_CON_DIV_DISPAUD_APB,
+ CLK_CON_DIV_DISPAUD_DECON_VCLK,
+ CLK_CON_DIV_DISPAUD_DECON_ECLK,
+ CLK_CON_DIV_DISPAUD_MI2S,
+ CLK_CON_DIV_DISPAUD_MIXER,
+ CLK_CON_GAT_DISPAUD_BUS,
+ CLK_CON_GAT_DISPAUD_BUS_DISP,
+ CLK_CON_GAT_DISPAUD_BUS_PPMU,
+ CLK_CON_GAT_DISPAUD_APB_AUD,
+ CLK_CON_GAT_DISPAUD_APB_AUD_AMP,
+ CLK_CON_GAT_DISPAUD_APB_DISP,
+ CLK_CON_GAT_DISPAUD_DECON_VCLK,
+ CLK_CON_GAT_DISPAUD_DECON_ECLK,
+ CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI,
+ CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI,
+ CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK,
+ CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S,
+ CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN,
+ CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK,
+ CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN,
+};
+
+static const struct samsung_fixed_rate_clock dispaud_fixed_clks[] __initconst = {
+ FRATE(0, "frat_dispaud_audiocdclk0", NULL, 0, 100000000),
+ FRATE(0, "frat_dispaud_mixer_bclk_bt", NULL, 0, 12500000),
+ FRATE(0, "frat_dispaud_mixer_bclk_cp", NULL, 0, 12500000),
+ FRATE(0, "frat_dispaud_mixer_bclk_fm", NULL, 0, 12500000),
+ FRATE(0, "frat_dispaud_mixer_sclk_ap", NULL, 0, 12500000),
+ FRATE(0, "frat_dispaud_mipiphy_rxclkesc0", NULL, 0, 188000000),
+ FRATE(0, "frat_dispaud_mipiphy_txbyteclkhs", NULL, 0, 188000000),
+};
+
+static const struct samsung_pll_clock dispaud_pll_clks[] __initconst = {
+ PLL(pll_1417x, CLK_FOUT_DISPAUD_AUD_PLL, "fout_dispaud_aud_pll",
+ "oscclk", PLL_LOCKTIME_DISPAUD_AUD_PLL, PLL_CON0_DISPAUD_AUD_PLL,
+ NULL),
+ PLL(pll_1417x, CLK_FOUT_DISPAUD_PLL, "fout_dispaud_pll", "oscclk",
+ PLL_LOCKTIME_DISPAUD_PLL, PLL_CON0_DISPAUD_PLL, NULL),
+};
+
+/* List of parent clocks for muxes in CMU_DISPAUD */
+PNAME(mout_dispaud_bus_user_p) = { "oscclk", "gout_mif_cmu_dispaud_bus" };
+PNAME(mout_dispaud_decon_eclk_user_p) = { "oscclk",
+ "gout_mif_cmu_dispaud_decon_eclk" };
+PNAME(mout_dispaud_decon_vclk_user_p) = { "oscclk",
+ "gout_mif_cmu_dispaud_decon_vclk" };
+PNAME(mout_dispaud_decon_eclk_p) = { "gout_dispaud_mux_decon_eclk_user",
+ "gout_dispaud_mux_pll_con" };
+PNAME(mout_dispaud_decon_vclk_p) = { "gout_dispaud_mux_decon_vclk_user",
+ "gout_dispaud_mux_pll_con" };
+PNAME(mout_dispaud_mi2s_p) = { "gout_dispaud_mux_aud_pll_con",
+ "frat_dispaud_audiocdclk0" };
+
+static const struct samsung_mux_clock dispaud_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_DISPAUD_BUS_USER, "mout_dispaud_bus_user",
+ mout_dispaud_bus_user_p, CLK_CON_MUX_DISPAUD_BUS_USER, 12, 1),
+ MUX(CLK_MOUT_DISPAUD_DECON_ECLK_USER, "mout_dispaud_decon_eclk_user",
+ mout_dispaud_decon_eclk_user_p, CLK_CON_MUX_DISPAUD_DECON_ECLK_USER,
+ 12, 1),
+ MUX(CLK_MOUT_DISPAUD_DECON_VCLK_USER, "mout_dispaud_decon_vclk_user",
+ mout_dispaud_decon_vclk_user_p, CLK_CON_MUX_DISPAUD_DECON_VCLK_USER,
+ 12, 1),
+ MUX(CLK_MOUT_DISPAUD_DECON_ECLK, "mout_dispaud_decon_eclk",
+ mout_dispaud_decon_eclk_p, CLK_CON_MUX_DISPAUD_DECON_ECLK, 12, 1),
+ MUX(CLK_MOUT_DISPAUD_DECON_VCLK, "mout_dispaud_decon_vclk",
+ mout_dispaud_decon_vclk_p, CLK_CON_MUX_DISPAUD_DECON_VCLK, 12, 1),
+ MUX(CLK_MOUT_DISPAUD_MI2S, "mout_dispaud_mi2s", mout_dispaud_mi2s_p,
+ CLK_CON_MUX_DISPAUD_MI2S, 12, 1),
+};
+
+static const struct samsung_div_clock dispaud_div_clks[] __initconst = {
+ DIV(CLK_DOUT_DISPAUD_APB, "dout_dispaud_apb",
+ "gout_dispaud_mux_bus_user", CLK_CON_DIV_DISPAUD_APB, 0, 2),
+ DIV(CLK_DOUT_DISPAUD_DECON_ECLK, "dout_dispaud_decon_eclk",
+ "gout_dispaud_mux_decon_eclk", CLK_CON_DIV_DISPAUD_DECON_ECLK, 0, 3),
+ DIV(CLK_DOUT_DISPAUD_DECON_VCLK, "dout_dispaud_decon_vclk",
+ "gout_dispaud_mux_decon_vclk", CLK_CON_DIV_DISPAUD_DECON_VCLK, 0, 3),
+ DIV(CLK_DOUT_DISPAUD_MI2S, "dout_dispaud_mi2s", "gout_dispaud_mux_mi2s",
+ CLK_CON_DIV_DISPAUD_MI2S, 0, 4),
+ DIV(CLK_DOUT_DISPAUD_MIXER, "dout_dispaud_mixer",
+ "gout_dispaud_mux_aud_pll_con", CLK_CON_DIV_DISPAUD_MIXER, 0, 4),
+};
+
+static const struct samsung_gate_clock dispaud_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_DISPAUD_BUS, "gout_dispaud_bus",
+ "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS, 0,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_BUS_DISP, "gout_dispaud_bus_disp",
+ "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS_DISP, 2,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_BUS_PPMU, "gout_dispaud_bus_ppmu",
+ "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS_PPMU, 3,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_APB_AUD, "gout_dispaud_apb_aud",
+ "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_AUD, 2,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_APB_AUD_AMP, "gout_dispaud_apb_aud_amp",
+ "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_AUD_AMP, 3,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_APB_DISP, "gout_dispaud_apb_disp",
+ "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_DISP, 1,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN,
+ "gout_dispaud_con_aud_i2s_bclk_bt_in",
+ "frat_dispaud_mixer_bclk_bt",
+ CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN, 0, CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN,
+ "gout_dispaud_con_aud_i2s_bclk_fm_in",
+ "frat_dispaud_mixer_bclk_fm",
+ CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN, 0, CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_DISPAUD_CON_CP2AUD_BCK, "gout_dispaud_con_cp2aud_bck",
+ "frat_dispaud_mixer_bclk_cp", CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK,
+ 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S,
+ "gout_dispaud_con_ext2aud_bck_gpio_i2s",
+ "frat_dispaud_mixer_sclk_ap",
+ CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_DECON_ECLK, "gout_dispaud_decon_eclk",
+ "dout_dispaud_decon_eclk", CLK_CON_GAT_DISPAUD_DECON_ECLK, 0,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_DECON_VCLK, "gout_dispaud_decon_vclk",
+ "dout_dispaud_decon_vclk", CLK_CON_GAT_DISPAUD_DECON_VCLK, 0,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI,
+ "gout_dispaud_mi2s_amp_i2scodclki", "dout_dispaud_mi2s",
+ CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI,
+ "gout_dispaud_mi2s_aud_i2scodclki", "dout_dispaud_mi2s",
+ CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK, "gout_dispaud_mixer_aud_sysclk",
+ "dout_dispaud_mixer", CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_AUD_PLL, "gout_dispaud_mux_aud_pll",
+ "gout_dispaud_mux_aud_pll_con", CLK_CON_GAT_DISPAUD_MUX_AUD_PLL,
+ 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON, "gout_dispaud_mux_aud_pll_con",
+ "fout_dispaud_aud_pll", CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_BUS_USER, "gout_dispaud_mux_bus_user",
+ "mout_dispaud_bus_user", CLK_CON_GAT_DISPAUD_MUX_BUS_USER, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER,
+ "gout_dispaud_mux_decon_eclk_user", "mout_dispaud_decon_eclk_user",
+ CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER,
+ "gout_dispaud_mux_decon_vclk_user", "mout_dispaud_decon_vclk_user",
+ CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER,
+ "gout_dispaud_mux_mipiphy_rxclkesc0_user",
+ "gout_dispaud_mux_mipiphy_rxclkesc0_user_con",
+ CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER, 21, CLK_IS_CRITICAL
+ | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON,
+ "gout_dispaud_mux_mipiphy_rxclkesc0_user_con",
+ "frat_dispaud_mipiphy_rxclkesc0",
+ CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER,
+ "gout_dispaud_mux_mipiphy_txbyteclkhs_user",
+ "gout_dispaud_mux_mipiphy_txbyteclkhs_user_con",
+ CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON,
+ "gout_dispaud_mux_mipiphy_txbyteclkhs_user_con",
+ "frat_dispaud_mipiphy_txbyteclkhs",
+ CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_DECON_ECLK, "gout_dispaud_mux_decon_eclk",
+ "mout_dispaud_decon_eclk", CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_DECON_VCLK, "gout_dispaud_mux_decon_vclk",
+ "mout_dispaud_decon_vclk", CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_MI2S, "gout_dispaud_mux_mi2s",
+ "mout_dispaud_mi2s", CLK_CON_GAT_DISPAUD_MUX_MI2S, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_PLL, "gout_dispaud_mux_pll",
+ "gout_dispaud_mux_pll_con", CLK_CON_GAT_DISPAUD_MUX_PLL, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_DISPAUD_MUX_PLL_CON, "gout_dispaud_mux_pll_con",
+ "fout_dispaud_pll", CLK_CON_GAT_DISPAUD_MUX_PLL_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info dispaud_cmu_info __initconst = {
+ .fixed_clks = dispaud_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(dispaud_fixed_clks),
+ .pll_clks = dispaud_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(dispaud_pll_clks),
+ .mux_clks = dispaud_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(dispaud_mux_clks),
+ .div_clks = dispaud_div_clks,
+ .nr_div_clks = ARRAY_SIZE(dispaud_div_clks),
+ .gate_clks = dispaud_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(dispaud_gate_clks),
+ .clk_regs = dispaud_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(dispaud_clk_regs),
+ .nr_clk_ids = DISPAUD_NR_CLK,
+};
+
+/*
+ * Register offsets for CMU_FSYS (0x13730000)
+ */
+#define PLL_LOCKTIME_FSYS_USB_PLL 0x0000
+#define PLL_CON0_FSYS_USB_PLL 0x0100
+#define CLK_CON_GAT_FSYS_MUX_USB_PLL 0x0200
+#define CLK_CON_GAT_FSYS_MUX_USB_PLL_CON 0x0200
+#define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 0x0230
+#define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 0x0230
+#define CLK_CON_GAT_FSYS_BUSP3_HCLK 0x0804
+#define CLK_CON_GAT_FSYS_MMC0_ACLK 0x0804
+#define CLK_CON_GAT_FSYS_MMC1_ACLK 0x0804
+#define CLK_CON_GAT_FSYS_MMC2_ACLK 0x0804
+#define CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0 0x0804
+#define CLK_CON_GAT_FSYS_PPMU_ACLK 0x0804
+#define CLK_CON_GAT_FSYS_PPMU_PCLK 0x0804
+#define CLK_CON_GAT_FSYS_SROMC_HCLK 0x0804
+#define CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK 0x0804
+#define CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD 0x0804
+#define CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL 0x0804
+#define CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK 0x0828
+
+static const unsigned long fsys_clk_regs[] __initconst = {
+ PLL_LOCKTIME_FSYS_USB_PLL,
+ PLL_CON0_FSYS_USB_PLL,
+ CLK_CON_GAT_FSYS_MUX_USB_PLL,
+ CLK_CON_GAT_FSYS_MUX_USB_PLL_CON,
+ CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER,
+ CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON,
+ CLK_CON_GAT_FSYS_BUSP3_HCLK,
+ CLK_CON_GAT_FSYS_MMC0_ACLK,
+ CLK_CON_GAT_FSYS_MMC1_ACLK,
+ CLK_CON_GAT_FSYS_MMC2_ACLK,
+ CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0,
+ CLK_CON_GAT_FSYS_PPMU_ACLK,
+ CLK_CON_GAT_FSYS_PPMU_PCLK,
+ CLK_CON_GAT_FSYS_SROMC_HCLK,
+ CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK,
+ CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD,
+ CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL,
+ CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK,
+};
+
+static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
+ FRATE(0, "frat_fsys_usb20drd_phyclock", NULL, 0, 60000000),
+};
+
+static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
+ PLL(pll_1417x, CLK_FOUT_FSYS_USB_PLL, "fout_fsys_usb_pll", "oscclk",
+ PLL_LOCKTIME_FSYS_USB_PLL, PLL_CON0_FSYS_USB_PLL, NULL),
+};
+
+static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_FSYS_BUSP3_HCLK, "gout_fsys_busp3_hclk",
+ "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_BUSP3_HCLK, 2,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_MMC0_ACLK, "gout_fsys_mmc0_aclk",
+ "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC0_ACLK, 8,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_MMC1_ACLK, "gout_fsys_mmc1_aclk",
+ "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC1_ACLK, 9,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_MMC2_ACLK, "gout_fsys_mmc2_aclk",
+ "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC2_ACLK, 10,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0, "gout_fsys_pdma0_aclk_pdma0",
+ "gout_fsys_upsizer_bus1_aclk", CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0,
+ 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_PPMU_ACLK, "gout_fsys_ppmu_aclk",
+ "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_PPMU_ACLK, 17,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_PPMU_PCLK, "gout_fsys_ppmu_pclk",
+ "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_PPMU_PCLK, 18,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_SROMC_HCLK, "gout_fsys_sromc_hclk",
+ "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_SROMC_HCLK, 6,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK, "gout_fsys_upsizer_bus1_aclk",
+ "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK, 12,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD, "gout_fsys_usb20drd_aclk_hsdrd",
+ "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD, 20,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL,
+ "gout_fsys_usb20drd_hclk_usb20_ctrl", "gout_fsys_busp3_hclk",
+ CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK,
+ "gout_fsys_usb20drd_hsdrd_ref_clk",
+ "gout_mif_cmu_fsys_usb20drd_refclk",
+ CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER,
+ "gout_fsys_mux_usb20drd_phyclock_user",
+ "gout_fsys_mux_usb20drd_phyclock_user_con",
+ CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON,
+ "gout_fsys_mux_usb20drd_phyclock_user_con",
+ "frat_fsys_usb20drd_phyclock",
+ CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_MUX_USB_PLL, "gout_fsys_mux_usb_pll",
+ "gout_fsys_mux_usb_pll_con", CLK_CON_GAT_FSYS_MUX_USB_PLL, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS_MUX_USB_PLL_CON, "gout_fsys_mux_usb_pll_con",
+ "fout_fsys_usb_pll", CLK_CON_GAT_FSYS_MUX_USB_PLL_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info fsys_cmu_info __initconst = {
+ .fixed_clks = fsys_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
+ .pll_clks = fsys_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(fsys_pll_clks),
+ .gate_clks = fsys_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
+ .clk_regs = fsys_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
+ .nr_clk_ids = FSYS_NR_CLK,
+};
+
+/*
+ * Register offsets for CMU_G3D (0x11460000)
+ */
+#define PLL_LOCKTIME_G3D_PLL 0x0000
+#define PLL_CON0_G3D_PLL 0x0100
+#define CLK_CON_GAT_G3D_MUX_PLL 0x0200
+#define CLK_CON_GAT_G3D_MUX_PLL_CON 0x0200
+#define CLK_CON_GAT_G3D_MUX_SWITCH_USER 0x0204
+#define CLK_CON_MUX_G3D_SWITCH_USER 0x0204
+#define CLK_CON_GAT_G3D_MUX 0x0208
+#define CLK_CON_MUX_G3D 0x0208
+#define CLK_CON_DIV_G3D_BUS 0x0400
+#define CLK_CON_DIV_G3D_APB 0x0404
+#define CLK_CON_GAT_G3D_ASYNCS_D0_CLK 0x0804
+#define CLK_CON_GAT_G3D_ASYNC_PCLKM 0x0804
+#define CLK_CON_GAT_G3D_CLK 0x0804
+#define CLK_CON_GAT_G3D_PPMU_ACLK 0x0804
+#define CLK_CON_GAT_G3D_QE_ACLK 0x0804
+#define CLK_CON_GAT_G3D_PPMU_PCLK 0x0808
+#define CLK_CON_GAT_G3D_QE_PCLK 0x0808
+#define CLK_CON_GAT_G3D_SYSREG_PCLK 0x0808
+
+static const unsigned long g3d_clk_regs[] __initconst = {
+ PLL_LOCKTIME_G3D_PLL,
+ PLL_CON0_G3D_PLL,
+ CLK_CON_GAT_G3D_MUX_PLL,
+ CLK_CON_GAT_G3D_MUX_PLL_CON,
+ CLK_CON_GAT_G3D_MUX_SWITCH_USER,
+ CLK_CON_MUX_G3D_SWITCH_USER,
+ CLK_CON_GAT_G3D_MUX,
+ CLK_CON_MUX_G3D,
+ CLK_CON_DIV_G3D_BUS,
+ CLK_CON_DIV_G3D_APB,
+ CLK_CON_GAT_G3D_ASYNCS_D0_CLK,
+ CLK_CON_GAT_G3D_ASYNC_PCLKM,
+ CLK_CON_GAT_G3D_CLK,
+ CLK_CON_GAT_G3D_PPMU_ACLK,
+ CLK_CON_GAT_G3D_QE_ACLK,
+ CLK_CON_GAT_G3D_PPMU_PCLK,
+ CLK_CON_GAT_G3D_QE_PCLK,
+ CLK_CON_GAT_G3D_SYSREG_PCLK,
+};
+
+static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
+ PLL(pll_1417x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
+ PLL_LOCKTIME_G3D_PLL, PLL_CON0_G3D_PLL, NULL),
+};
+
+/* List of parent clocks for muxes in CMU_G3D */
+PNAME(mout_g3d_switch_user_p) = { "oscclk", "gout_mif_cmu_g3d_switch" };
+PNAME(mout_g3d_p) = { "gout_g3d_mux_pll_con",
+ "gout_g3d_mux_switch_user" };
+
+static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
+ mout_g3d_switch_user_p, CLK_CON_MUX_G3D_SWITCH_USER, 12, 1),
+ MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, CLK_CON_MUX_G3D, 12, 1),
+};
+
+static const struct samsung_div_clock g3d_div_clks[] __initconst = {
+ DIV(CLK_DOUT_G3D_APB, "dout_g3d_apb", "dout_g3d_bus",
+ CLK_CON_DIV_G3D_APB, 0, 3),
+ DIV(CLK_DOUT_G3D_BUS, "dout_g3d_bus", "gout_g3d_mux",
+ CLK_CON_DIV_G3D_BUS, 0, 3),
+};
+
+static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_G3D_ASYNCS_D0_CLK, "gout_g3d_asyncs_d0_clk",
+ "dout_g3d_bus", CLK_CON_GAT_G3D_ASYNCS_D0_CLK, 1, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_G3D_ASYNC_PCLKM, "gout_g3d_async_pclkm", "dout_g3d_bus",
+ CLK_CON_GAT_G3D_ASYNC_PCLKM, 0, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_G3D_CLK, "gout_g3d_clk", "dout_g3d_bus",
+ CLK_CON_GAT_G3D_CLK, 6, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_G3D_PPMU_ACLK, "gout_g3d_ppmu_aclk", "dout_g3d_bus",
+ CLK_CON_GAT_G3D_PPMU_ACLK, 7, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_G3D_PPMU_PCLK, "gout_g3d_ppmu_pclk", "dout_g3d_apb",
+ CLK_CON_GAT_G3D_PPMU_PCLK, 4, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_G3D_QE_ACLK, "gout_g3d_qe_aclk", "dout_g3d_bus",
+ CLK_CON_GAT_G3D_QE_ACLK, 8, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_G3D_QE_PCLK, "gout_g3d_qe_pclk", "dout_g3d_apb",
+ CLK_CON_GAT_G3D_QE_PCLK, 5, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_apb",
+ CLK_CON_GAT_G3D_SYSREG_PCLK, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_G3D_MUX_SWITCH_USER, "gout_g3d_mux_switch_user",
+ "mout_g3d_switch_user", CLK_CON_GAT_G3D_MUX_SWITCH_USER, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_G3D_MUX, "gout_g3d_mux", "mout_g3d", CLK_CON_GAT_G3D_MUX,
+ 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_G3D_MUX_PLL, "gout_g3d_mux_pll", "gout_g3d_mux_pll_con",
+ CLK_CON_GAT_G3D_MUX_PLL, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_G3D_MUX_PLL_CON, "gout_g3d_mux_pll_con", "fout_g3d_pll",
+ CLK_CON_GAT_G3D_MUX_PLL_CON, 12, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info g3d_cmu_info __initconst = {
+ .pll_clks = g3d_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
+ .mux_clks = g3d_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
+ .div_clks = g3d_div_clks,
+ .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
+ .gate_clks = g3d_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
+ .clk_regs = g3d_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
+ .nr_clk_ids = G3D_NR_CLK,
+};
+
+/*
+ * Register offsets for CMU_ISP (0x144d0000)
+ */
+#define PLL_LOCKTIME_ISP_PLL 0x0000
+#define PLL_CON0_ISP_PLL 0x0100
+#define CLK_CON_GAT_ISP_MUX_PLL 0x0200
+#define CLK_CON_GAT_ISP_MUX_PLL_CON 0x0200
+#define CLK_CON_GAT_ISP_MUX_VRA_USER 0x0210
+#define CLK_CON_MUX_ISP_VRA_USER 0x0210
+#define CLK_CON_GAT_ISP_MUX_CAM_USER 0x0214
+#define CLK_CON_MUX_ISP_CAM_USER 0x0214
+#define CLK_CON_GAT_ISP_MUX_USER 0x0218
+#define CLK_CON_MUX_ISP_USER 0x0218
+#define CLK_CON_GAT_ISP_MUX_VRA 0x0220
+#define CLK_CON_MUX_ISP_VRA 0x0220
+#define CLK_CON_GAT_ISP_MUX_CAM 0x0224
+#define CLK_CON_MUX_ISP_CAM 0x0224
+#define CLK_CON_GAT_ISP_MUX_ISP 0x0228
+#define CLK_CON_MUX_ISP_ISP 0x0228
+#define CLK_CON_GAT_ISP_MUX_ISPD 0x022c
+#define CLK_CON_MUX_ISP_ISPD 0x022c
+#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 0x0230
+#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 0x0230
+#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 0x0234
+#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 0x0234
+#define CLK_CON_DIV_ISP_APB 0x0400
+#define CLK_CON_DIV_ISP_CAM_HALF 0x0404
+#define CLK_CON_GAT_ISP_VRA 0x0810
+#define CLK_CON_GAT_ISP_ISPD 0x0818
+#define CLK_CON_GAT_ISP_ISPD_PPMU 0x0818
+#define CLK_CON_GAT_ISP_CAM 0x081c
+#define CLK_CON_GAT_ISP_CAM_HALF 0x0820
+
+static const unsigned long isp_clk_regs[] __initconst = {
+ PLL_LOCKTIME_ISP_PLL,
+ PLL_CON0_ISP_PLL,
+ CLK_CON_GAT_ISP_MUX_PLL,
+ CLK_CON_GAT_ISP_MUX_PLL_CON,
+ CLK_CON_GAT_ISP_MUX_VRA_USER,
+ CLK_CON_MUX_ISP_VRA_USER,
+ CLK_CON_GAT_ISP_MUX_CAM_USER,
+ CLK_CON_MUX_ISP_CAM_USER,
+ CLK_CON_GAT_ISP_MUX_USER,
+ CLK_CON_MUX_ISP_USER,
+ CLK_CON_GAT_ISP_MUX_VRA,
+ CLK_CON_MUX_ISP_VRA,
+ CLK_CON_GAT_ISP_MUX_CAM,
+ CLK_CON_MUX_ISP_CAM,
+ CLK_CON_GAT_ISP_MUX_ISP,
+ CLK_CON_MUX_ISP_ISP,
+ CLK_CON_GAT_ISP_MUX_ISPD,
+ CLK_CON_MUX_ISP_ISPD,
+ CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER,
+ CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON,
+ CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER,
+ CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON,
+ CLK_CON_DIV_ISP_APB,
+ CLK_CON_DIV_ISP_CAM_HALF,
+ CLK_CON_GAT_ISP_VRA,
+ CLK_CON_GAT_ISP_ISPD,
+ CLK_CON_GAT_ISP_ISPD_PPMU,
+ CLK_CON_GAT_ISP_CAM,
+ CLK_CON_GAT_ISP_CAM_HALF,
+};
+
+static const struct samsung_fixed_rate_clock isp_fixed_clks[] __initconst = {
+ FRATE(0, "frat_isp_rxbyteclkhs0_sensor0", NULL, 0, 188000000),
+ FRATE(0, "frat_isp_rxbyteclkhs0_sensor1", NULL, 0, 188000000),
+};
+
+static const struct samsung_pll_clock isp_pll_clks[] __initconst = {
+ PLL(pll_1417x, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
+ PLL_LOCKTIME_ISP_PLL, PLL_CON0_ISP_PLL, NULL),
+};
+
+/* List of parent clocks for muxes in CMU_ISP */
+PNAME(mout_isp_cam_user_p) = { "oscclk", "gout_mif_cmu_isp_cam" };
+PNAME(mout_isp_user_p) = { "oscclk", "gout_mif_cmu_isp_isp" };
+PNAME(mout_isp_vra_user_p) = { "oscclk", "gout_mif_cmu_isp_vra" };
+PNAME(mout_isp_cam_p) = { "gout_isp_mux_cam_user",
+ "gout_isp_mux_pll_con" };
+PNAME(mout_isp_isp_p) = { "gout_isp_mux_user", "gout_isp_mux_pll_con" };
+PNAME(mout_isp_ispd_p) = { "gout_isp_mux_vra", "gout_isp_mux_cam" };
+PNAME(mout_isp_vra_p) = { "gout_isp_mux_vra_user",
+ "gout_isp_mux_pll_con" };
+
+static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_ISP_CAM_USER, "mout_isp_cam_user", mout_isp_cam_user_p,
+ CLK_CON_MUX_ISP_CAM_USER, 12, 1),
+ MUX(CLK_MOUT_ISP_USER, "mout_isp_user", mout_isp_user_p,
+ CLK_CON_MUX_ISP_USER, 12, 1),
+ MUX(CLK_MOUT_ISP_VRA_USER, "mout_isp_vra_user", mout_isp_vra_user_p,
+ CLK_CON_MUX_ISP_VRA_USER, 12, 1),
+ MUX(CLK_MOUT_ISP_CAM, "mout_isp_cam", mout_isp_cam_p,
+ CLK_CON_MUX_ISP_CAM, 12, 1),
+ MUX(CLK_MOUT_ISP_ISP, "mout_isp_isp", mout_isp_isp_p,
+ CLK_CON_MUX_ISP_ISP, 12, 1),
+ MUX(CLK_MOUT_ISP_ISPD, "mout_isp_ispd", mout_isp_ispd_p,
+ CLK_CON_MUX_ISP_ISPD, 12, 1),
+ MUX(CLK_MOUT_ISP_VRA, "mout_isp_vra", mout_isp_vra_p,
+ CLK_CON_MUX_ISP_VRA, 12, 1),
+};
+
+static const struct samsung_div_clock isp_div_clks[] __initconst = {
+ DIV(CLK_DOUT_ISP_APB, "dout_isp_apb", "gout_isp_mux_vra",
+ CLK_CON_DIV_ISP_APB, 0, 2),
+ DIV(CLK_DOUT_ISP_CAM_HALF, "dout_isp_cam_half", "gout_isp_mux_cam",
+ CLK_CON_DIV_ISP_CAM_HALF, 0, 2),
+};
+
+static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_ISP_CAM, "gout_isp_cam", "gout_isp_mux_cam",
+ CLK_CON_GAT_ISP_CAM, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_CAM_HALF, "gout_isp_cam_half", "dout_isp_cam_half",
+ CLK_CON_GAT_ISP_CAM_HALF, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_ISPD, "gout_isp_ispd", "gout_isp_mux_ispd",
+ CLK_CON_GAT_ISP_ISPD, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_ISPD_PPMU, "gout_isp_ispd_ppmu", "gout_isp_mux_ispd",
+ CLK_CON_GAT_ISP_ISPD_PPMU, 1, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_VRA, "gout_isp_vra", "gout_isp_mux_vra",
+ CLK_CON_GAT_ISP_VRA, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_CAM_USER, "gout_isp_mux_cam_user",
+ "mout_isp_cam_user", CLK_CON_GAT_ISP_MUX_CAM_USER, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_USER, "gout_isp_mux_user", "mout_isp_user",
+ CLK_CON_GAT_ISP_MUX_USER, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_VRA_USER, "gout_isp_mux_vra_user",
+ "mout_isp_vra_user", CLK_CON_GAT_ISP_MUX_VRA_USER, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER,
+ "gout_isp_mux_rxbyteclkhs0_sensor1_user",
+ "gout_isp_mux_rxbyteclkhs0_sensor1_user_con",
+ CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER, 21, CLK_IS_CRITICAL
+ | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON,
+ "gout_isp_mux_rxbyteclkhs0_sensor1_user_con",
+ "frat_isp_rxbyteclkhs0_sensor1",
+ CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER,
+ "gout_isp_mux_rxbyteclkhs0_sensor0_user",
+ "gout_isp_mux_rxbyteclkhs0_sensor0_user_con",
+ CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER, 21, CLK_IS_CRITICAL
+ | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON,
+ "gout_isp_mux_rxbyteclkhs0_sensor0_user_con",
+ "frat_isp_rxbyteclkhs0_sensor0",
+ CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_CAM, "gout_isp_mux_cam", "mout_isp_cam",
+ CLK_CON_GAT_ISP_MUX_CAM, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_ISP_MUX_ISP, "gout_isp_mux_isp", "mout_isp_isp",
+ CLK_CON_GAT_ISP_MUX_ISP, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_ISP_MUX_ISPD, "gout_isp_mux_ispd", "mout_isp_ispd",
+ CLK_CON_GAT_ISP_MUX_ISPD, 21, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_ISP_MUX_VRA, "gout_isp_mux_vra", "mout_isp_vra",
+ CLK_CON_GAT_ISP_MUX_VRA, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_ISP_MUX_PLL, "gout_isp_mux_pll", "gout_isp_mux_pll_con",
+ CLK_CON_GAT_ISP_MUX_PLL, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ 0),
+ GATE(CLK_GOUT_ISP_MUX_PLL_CON, "gout_isp_mux_pll_con", "fout_isp_pll",
+ CLK_CON_GAT_ISP_MUX_PLL_CON, 12, CLK_IS_CRITICAL |
+ CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info isp_cmu_info __initconst = {
+ .fixed_clks = isp_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(isp_fixed_clks),
+ .pll_clks = isp_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(isp_pll_clks),
+ .mux_clks = isp_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
+ .div_clks = isp_div_clks,
+ .nr_div_clks = ARRAY_SIZE(isp_div_clks),
+ .gate_clks = isp_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
+ .clk_regs = isp_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
+ .nr_clk_ids = ISP_NR_CLK,
+};
+
+/*
+ * Register offsets for CMU_MFCMSCL (0x12cb0000)
+ */
+#define CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER 0x0200
+#define CLK_CON_MUX_MFCMSCL_MSCL_USER 0x0200
+#define CLK_CON_GAT_MFCMSCL_MUX_MFC_USER 0x0204
+#define CLK_CON_MUX_MFCMSCL_MFC_USER 0x0204
+#define CLK_CON_DIV_MFCMSCL_APB 0x0400
+#define CLK_CON_GAT_MFCMSCL_MSCL 0x0804
+#define CLK_CON_GAT_MFCMSCL_MSCL_BI 0x0804
+#define CLK_CON_GAT_MFCMSCL_MSCL_D 0x0804
+#define CLK_CON_GAT_MFCMSCL_MSCL_JPEG 0x0804
+#define CLK_CON_GAT_MFCMSCL_MSCL_POLY 0x0804
+#define CLK_CON_GAT_MFCMSCL_MSCL_PPMU 0x0804
+#define CLK_CON_GAT_MFCMSCL_MFC 0x0808
+
+static const unsigned long mfcmscl_clk_regs[] __initconst = {
+ CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER,
+ CLK_CON_MUX_MFCMSCL_MSCL_USER,
+ CLK_CON_GAT_MFCMSCL_MUX_MFC_USER,
+ CLK_CON_MUX_MFCMSCL_MFC_USER,
+ CLK_CON_DIV_MFCMSCL_APB,
+ CLK_CON_GAT_MFCMSCL_MSCL,
+ CLK_CON_GAT_MFCMSCL_MSCL_BI,
+ CLK_CON_GAT_MFCMSCL_MSCL_D,
+ CLK_CON_GAT_MFCMSCL_MSCL_JPEG,
+ CLK_CON_GAT_MFCMSCL_MSCL_POLY,
+ CLK_CON_GAT_MFCMSCL_MSCL_PPMU,
+ CLK_CON_GAT_MFCMSCL_MFC,
+};
+
+/* List of parent clocks for muxes in CMU_MFCMSCL */
+PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "gout_mif_cmu_mfcmscl_mfc" };
+PNAME(mout_mfcmscl_mscl_user_p) = { "oscclk", "gout_mif_cmu_mfcmscl_mscl" };
+
+static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
+ mout_mfcmscl_mfc_user_p, CLK_CON_MUX_MFCMSCL_MFC_USER, 12, 1),
+ MUX(CLK_MOUT_MFCMSCL_MSCL_USER, "mout_mfcmscl_mscl_user",
+ mout_mfcmscl_mscl_user_p, CLK_CON_MUX_MFCMSCL_MSCL_USER, 12, 1),
+};
+
+static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
+ DIV(CLK_DOUT_MFCMSCL_APB, "dout_mfcmscl_apb",
+ "gout_mfcmscl_mux_mscl_user", CLK_CON_DIV_MFCMSCL_APB, 0, 2),
+};
+
+static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc",
+ "gout_mfcmscl_mux_mfc_user", CLK_CON_GAT_MFCMSCL_MFC, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MFCMSCL_MSCL, "gout_mfcmscl_mscl",
+ "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL, 0,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MFCMSCL_MSCL_BI, "gout_mfcmscl_mscl_bi",
+ "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_BI, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MFCMSCL_MSCL_D, "gout_mfcmscl_mscl_d",
+ "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL_D, 1,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MFCMSCL_MSCL_JPEG, "gout_mfcmscl_mscl_jpeg",
+ "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_JPEG, 2,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MFCMSCL_MSCL_POLY, "gout_mfcmscl_mscl_poly",
+ "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_POLY, 3,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MFCMSCL_MSCL_PPMU, "gout_mfcmscl_mscl_ppmu",
+ "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL_PPMU, 5,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MFCMSCL_MUX_MFC_USER, "gout_mfcmscl_mux_mfc_user",
+ "mout_mfcmscl_mfc_user", CLK_CON_GAT_MFCMSCL_MUX_MFC_USER, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_MFCMSCL_MUX_MSCL_USER, "gout_mfcmscl_mux_mscl_user",
+ "mout_mfcmscl_mscl_user", CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER, 21,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
+ .mux_clks = mfcmscl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
+ .div_clks = mfcmscl_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
+ .gate_clks = mfcmscl_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
+ .clk_regs = mfcmscl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
+ .nr_clk_ids = MFCMSCL_NR_CLK,
+};
+
+/*
+ * Register offsets for CMU_PERI (0x101f0000)
+ */
+#define CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK 0x0800
+#define CLK_CON_GAT_PERI_TMU_CPUCL0_CLK 0x0800
+#define CLK_CON_GAT_PERI_TMU_CPUCL1_CLK 0x0800
+#define CLK_CON_GAT_PERI_TMU_CLK 0x0800
+#define CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK 0x0810
+#define CLK_CON_GAT_PERI_GPIO2_PCLK 0x0810
+#define CLK_CON_GAT_PERI_GPIO5_PCLK 0x0810
+#define CLK_CON_GAT_PERI_GPIO6_PCLK 0x0810
+#define CLK_CON_GAT_PERI_GPIO7_PCLK 0x0810
+#define CLK_CON_GAT_PERI_HSI2C4_IPCLK 0x0810
+#define CLK_CON_GAT_PERI_HSI2C6_IPCLK 0x0810
+#define CLK_CON_GAT_PERI_HSI2C3_IPCLK 0x0810
+#define CLK_CON_GAT_PERI_HSI2C5_IPCLK 0x0810
+#define CLK_CON_GAT_PERI_HSI2C2_IPCLK 0x0810
+#define CLK_CON_GAT_PERI_HSI2C1_IPCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C0_PCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C4_PCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C5_PCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C6_PCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C7_PCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C8_PCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C3_PCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C2_PCLK 0x0810
+#define CLK_CON_GAT_PERI_I2C1_PCLK 0x0810
+#define CLK_CON_GAT_PERI_MCT_PCLK 0x0810
+#define CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0 0x0810
+#define CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK 0x0814
+#define CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK 0x0814
+#define CLK_CON_GAT_PERI_SFRIF_TMU_PCLK 0x0814
+#define CLK_CON_GAT_PERI_SPI0_PCLK 0x0814
+#define CLK_CON_GAT_PERI_SPI2_PCLK 0x0814
+#define CLK_CON_GAT_PERI_SPI1_PCLK 0x0814
+#define CLK_CON_GAT_PERI_SPI4_PCLK 0x0814
+#define CLK_CON_GAT_PERI_SPI3_PCLK 0x0814
+#define CLK_CON_GAT_PERI_UART1_PCLK 0x0814
+#define CLK_CON_GAT_PERI_UART2_PCLK 0x0814
+#define CLK_CON_GAT_PERI_UART0_PCLK 0x0814
+#define CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK 0x0814
+#define CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK 0x0814
+#define CLK_CON_GAT_PERI_UART1_EXT_UCLK 0x0830
+#define CLK_CON_GAT_PERI_UART2_EXT_UCLK 0x0834
+#define CLK_CON_GAT_PERI_UART0_EXT_UCLK 0x0838
+#define CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK 0x083c
+#define CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK 0x0840
+#define CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK 0x0844
+#define CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK 0x0848
+#define CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK 0x084c
+
+static const unsigned long peri_clk_regs[] __initconst = {
+ CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK,
+ CLK_CON_GAT_PERI_TMU_CPUCL0_CLK,
+ CLK_CON_GAT_PERI_TMU_CPUCL1_CLK,
+ CLK_CON_GAT_PERI_TMU_CLK,
+ CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK,
+ CLK_CON_GAT_PERI_GPIO2_PCLK,
+ CLK_CON_GAT_PERI_GPIO5_PCLK,
+ CLK_CON_GAT_PERI_GPIO6_PCLK,
+ CLK_CON_GAT_PERI_GPIO7_PCLK,
+ CLK_CON_GAT_PERI_HSI2C4_IPCLK,
+ CLK_CON_GAT_PERI_HSI2C6_IPCLK,
+ CLK_CON_GAT_PERI_HSI2C3_IPCLK,
+ CLK_CON_GAT_PERI_HSI2C5_IPCLK,
+ CLK_CON_GAT_PERI_HSI2C2_IPCLK,
+ CLK_CON_GAT_PERI_HSI2C1_IPCLK,
+ CLK_CON_GAT_PERI_I2C0_PCLK,
+ CLK_CON_GAT_PERI_I2C4_PCLK,
+ CLK_CON_GAT_PERI_I2C5_PCLK,
+ CLK_CON_GAT_PERI_I2C6_PCLK,
+ CLK_CON_GAT_PERI_I2C7_PCLK,
+ CLK_CON_GAT_PERI_I2C8_PCLK,
+ CLK_CON_GAT_PERI_I2C3_PCLK,
+ CLK_CON_GAT_PERI_I2C2_PCLK,
+ CLK_CON_GAT_PERI_I2C1_PCLK,
+ CLK_CON_GAT_PERI_MCT_PCLK,
+ CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0,
+ CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK,
+ CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK,
+ CLK_CON_GAT_PERI_SFRIF_TMU_PCLK,
+ CLK_CON_GAT_PERI_SPI0_PCLK,
+ CLK_CON_GAT_PERI_SPI2_PCLK,
+ CLK_CON_GAT_PERI_SPI1_PCLK,
+ CLK_CON_GAT_PERI_SPI4_PCLK,
+ CLK_CON_GAT_PERI_SPI3_PCLK,
+ CLK_CON_GAT_PERI_UART1_PCLK,
+ CLK_CON_GAT_PERI_UART2_PCLK,
+ CLK_CON_GAT_PERI_UART0_PCLK,
+ CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK,
+ CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK,
+ CLK_CON_GAT_PERI_UART1_EXT_UCLK,
+ CLK_CON_GAT_PERI_UART2_EXT_UCLK,
+ CLK_CON_GAT_PERI_UART0_EXT_UCLK,
+ CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK,
+ CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK,
+ CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK,
+ CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK,
+ CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK,
+};
+
+static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_PERI_BUSP1_PERIC0_HCLK, "gout_peri_busp1_peric0_hclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK, 3,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_GPIO2_PCLK, "gout_peri_gpio2_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO2_PCLK, 7,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_GPIO5_PCLK, "gout_peri_gpio5_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO5_PCLK, 8,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_GPIO6_PCLK, "gout_peri_gpio6_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO6_PCLK, 9,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_GPIO7_PCLK, "gout_peri_gpio7_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO7_PCLK, 10,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_HSI2C4_IPCLK, "gout_peri_hsi2c4_ipclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C4_IPCLK, 14,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_HSI2C6_IPCLK, "gout_peri_hsi2c6_ipclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_HSI2C6_IPCLK, 16,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_HSI2C3_IPCLK, "gout_peri_hsi2c3_ipclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C3_IPCLK, 13,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_HSI2C5_IPCLK, "gout_peri_hsi2c5_ipclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_HSI2C5_IPCLK, 15,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_HSI2C2_IPCLK, "gout_peri_hsi2c2_ipclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C2_IPCLK, 12,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_HSI2C1_IPCLK, "gout_peri_hsi2c1_ipclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C1_IPCLK, 11,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C0_PCLK, "gout_peri_i2c0_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C0_PCLK, 21,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C4_PCLK, "gout_peri_i2c4_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C4_PCLK, 17,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C5_PCLK, "gout_peri_i2c5_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C5_PCLK, 18,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C6_PCLK, "gout_peri_i2c6_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C6_PCLK, 19,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C7_PCLK, "gout_peri_i2c7_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C7_PCLK, 24,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C8_PCLK, "gout_peri_i2c8_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C8_PCLK, 25,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C3_PCLK, "gout_peri_i2c3_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C3_PCLK, 20,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C2_PCLK, "gout_peri_i2c2_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C2_PCLK, 22,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I2C1_PCLK, "gout_peri_i2c1_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C1_PCLK, 23,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_MCT_PCLK, "gout_peri_mct_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_MCT_PCLK, 26,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_PWM_MOTOR_OSCCLK, "gout_peri_pwm_motor_oscclk",
+ "oscclk", CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK, 2,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0, "gout_peri_pwm_motor_pclk_s0",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0, 29,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK,
+ "gout_peri_sfrif_tmu_cpucl0_pclk", "gout_mif_cmu_peri_bus",
+ CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK,
+ "gout_peri_sfrif_tmu_cpucl1_pclk", "gout_mif_cmu_peri_bus",
+ CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SFRIF_TMU_PCLK, "gout_peri_sfrif_tmu_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SFRIF_TMU_PCLK, 3,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI0_PCLK, "gout_peri_spi0_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI0_PCLK, 6,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI0_SPI_EXT_CLK, "gout_peri_spi0_spi_ext_clk",
+ "gout_mif_cmu_peri_spi0", CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI2_PCLK, "gout_peri_spi2_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI2_PCLK, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI2_SPI_EXT_CLK, "gout_peri_spi2_spi_ext_clk",
+ "gout_mif_cmu_peri_spi2", CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI1_PCLK, "gout_peri_spi1_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI1_PCLK, 5,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI1_SPI_EXT_CLK, "gout_peri_spi1_spi_ext_clk",
+ "gout_mif_cmu_peri_spi1", CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI4_PCLK, "gout_peri_spi4_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI4_PCLK, 8,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI4_SPI_EXT_CLK, "gout_peri_spi4_spi_ext_clk",
+ "gout_mif_cmu_peri_spi4", CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI3_PCLK, "gout_peri_spi3_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI3_PCLK, 7,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_SPI3_SPI_EXT_CLK, "gout_peri_spi3_spi_ext_clk",
+ "gout_mif_cmu_peri_spi3", CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_TMU_CPUCL0_CLK, "gout_peri_tmu_cpucl0_clk", "oscclk",
+ CLK_CON_GAT_PERI_TMU_CPUCL0_CLK, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_TMU_CPUCL1_CLK, "gout_peri_tmu_cpucl1_clk", "oscclk",
+ CLK_CON_GAT_PERI_TMU_CPUCL1_CLK, 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_TMU_CLK, "gout_peri_tmu_clk", "oscclk",
+ CLK_CON_GAT_PERI_TMU_CLK, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_UART1_EXT_UCLK, "gout_peri_uart1_ext_uclk",
+ "gout_mif_cmu_peri_uart1", CLK_CON_GAT_PERI_UART1_EXT_UCLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_UART1_PCLK, "gout_peri_uart1_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART1_PCLK, 11,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_UART2_EXT_UCLK, "gout_peri_uart2_ext_uclk",
+ "gout_mif_cmu_peri_uart2", CLK_CON_GAT_PERI_UART2_EXT_UCLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_UART2_PCLK, "gout_peri_uart2_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART2_PCLK, 12,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_UART0_EXT_UCLK, "gout_peri_uart0_ext_uclk",
+ "gout_mif_cmu_peri_uart0", CLK_CON_GAT_PERI_UART0_EXT_UCLK, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_UART0_PCLK, "gout_peri_uart0_pclk",
+ "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART0_PCLK, 10,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_WDT_CPUCL0_PCLK, "gout_peri_wdt_cpucl0_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK, 13,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_WDT_CPUCL1_PCLK, "gout_peri_wdt_cpucl1_pclk",
+ "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK, 14,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info peri_cmu_info __initconst = {
+ .gate_clks = peri_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
+ .clk_regs = peri_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
+ .nr_clk_ids = PERI_NR_CLK,
+};
+
+static int __init exynos7870_cmu_probe(struct platform_device *pdev)
+{
+ const struct samsung_cmu_info *info;
+ struct device *dev = &pdev->dev;
+
+ info = of_device_get_match_data(dev);
+ exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+ return 0;
+}
+
+static const struct of_device_id exynos7870_cmu_of_match[] = {
+ {
+ .compatible = "samsung,exynos7870-cmu-mif",
+ .data = &mif_cmu_info,
+ }, {
+ .compatible = "samsung,exynos7870-cmu-dispaud",
+ .data = &dispaud_cmu_info,
+ }, {
+ .compatible = "samsung,exynos7870-cmu-fsys",
+ .data = &fsys_cmu_info,
+ }, {
+ .compatible = "samsung,exynos7870-cmu-g3d",
+ .data = &g3d_cmu_info,
+ }, {
+ .compatible = "samsung,exynos7870-cmu-isp",
+ .data = &isp_cmu_info,
+ }, {
+ .compatible = "samsung,exynos7870-cmu-mfcmscl",
+ .data = &mfcmscl_cmu_info,
+ }, {
+ .compatible = "samsung,exynos7870-cmu-peri",
+ .data = &peri_cmu_info,
+ }, {
+ },
+};
+
+static struct platform_driver exynos7870_cmu_driver __refdata = {
+ .driver = {
+ .name = "exynos7870-cmu",
+ .of_match_table = exynos7870_cmu_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = exynos7870_cmu_probe,
+};
+
+static int __init exynos7870_cmu_init(void)
+{
+ return platform_driver_register(&exynos7870_cmu_driver);
+}
+core_initcall(exynos7870_cmu_init);
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support
2025-02-18 18:50 [PATCH v3 0/5] Introduce support for Exynos7870 clocks and PMU Kaustabh Chakraborty
` (3 preceding siblings ...)
2025-02-18 18:50 ` [PATCH v3 4/5] clk: samsung: add initial exynos7870 clock driver Kaustabh Chakraborty
@ 2025-02-18 18:50 ` Kaustabh Chakraborty
2025-02-19 8:11 ` Krzysztof Kozlowski
4 siblings, 1 reply; 18+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-18 18:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, Kaustabh Chakraborty
Exynos7870's CLKOUT registers are the same as Exynos5's. Add the PMU
compatible to the existing CLKOUT ID list.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
drivers/clk/samsung/clk-exynos-clkout.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
index 2ef5748c139b37ca5429b9071ee0e06f44fcf28e..9a31b1c311b45096f1d680b6724571854c08725c 100644
--- a/drivers/clk/samsung/clk-exynos-clkout.c
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -75,6 +75,9 @@ static const struct of_device_id exynos_clkout_ids[] = {
}, {
.compatible = "samsung,exynos5433-pmu",
.data = &exynos_clkout_exynos5,
+ }, {
+ .compatible = "samsung,exynos7870-pmu",
+ .data = &exynos_clkout_exynos5,
}, { }
};
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: clock: document exynos7870 clock driver CMU bindings
2025-02-18 18:50 ` [PATCH v3 2/5] dt-bindings: clock: document exynos7870 clock driver CMU bindings Kaustabh Chakraborty
@ 2025-02-19 8:05 ` Krzysztof Kozlowski
2025-02-19 8:10 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-19 8:05 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On Wed, Feb 19, 2025 at 12:20:29AM +0530, Kaustabh Chakraborty wrote:
> + Exynos7870 clock controller is comprised of several CMU units, generating
> + clocks for different domains. Those CMU units are modeled as separate device
> + tree nodes, and might depend on each other. The root clock in that root tree
> + is an external clock: OSCCLK (26 MHz). This external clock must be defined
> + as a fixed-rate clock in dts.
> +
> + Each clock is assigned an identifier and client nodes can use this identifier
> + to specify the clock which they consume. All clocks available for usage
> + in clock consumer nodes are defined as preprocessor macros in
> + 'dt-bindings/clock/exynos7870.h' header.
Full path and drop quotes
> +
> +properties:
> + compatible:
> + enum:
> + - samsung,exynos7870-cmu-mif
> + - samsung,exynos7870-cmu-dispaud
> + - samsung,exynos7870-cmu-fsys
> + - samsung,exynos7870-cmu-g3d
> + - samsung,exynos7870-cmu-isp
> + - samsung,exynos7870-cmu-mfcmscl
> + - samsung,exynos7870-cmu-peri
> +
> + clocks:
> + minItems: 1
> + maxItems: 10
> +
> + clock-names:
> + minItems: 1
> + maxItems: 10
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - "#clock-cells"
This goes after clock-names, to keep the same order. No need to repeat
old mistakes.
> + - clocks
> + - clock-names
> + - reg
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7870-cmu-mif
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> +
> + clock-names:
> + items:
> + - const: oscclk
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7870-cmu-dispaud
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_DISPAUD bus clock (from CMU_MIF)
> + - description: DECON external clock (from CMU_MIF)
> + - description: DECON vertical clock (from CMU_MIF)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: bus
> + - const: decon_eclk
> + - const: decon_vclk
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7870-cmu-fsys
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_FSYS bus clock (from CMU_MIF)
> + - description: USB20DRD clock (from CMU_MIF)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: bus
> + - const: usb20drd_refclk
Drop _refclk suffix
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-18 18:50 ` [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU Kaustabh Chakraborty
@ 2025-02-19 8:07 ` Krzysztof Kozlowski
2025-02-19 8:10 ` Krzysztof Kozlowski
2025-02-23 9:57 ` Krzysztof Kozlowski
1 sibling, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-19 8:07 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On Wed, Feb 19, 2025 at 12:20:28AM +0530, Kaustabh Chakraborty wrote:
> Add unique identifiers for exynos7870 clocks for every bank. It adds all
> clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
> CMU_PERI.
>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
> ---
> include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++++++++++
> 1 file changed, 324 insertions(+)
Again, you keep repeating some old patterns ignoring what was added
recently. This must match compatible, so missing vendor prefix.
Also squash the patch with the binding itself so you will see the
difference in names.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 3/5] dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible
2025-02-18 18:50 ` [PATCH v3 3/5] dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible Kaustabh Chakraborty
@ 2025-02-19 8:09 ` Krzysztof Kozlowski
2025-02-19 8:18 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-19 8:09 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On Wed, Feb 19, 2025 at 12:20:30AM +0530, Kaustabh Chakraborty wrote:
> Document the compatible string for the Exynos7870 PMU. It's compatible
> with the Exynos7 PMU design. It handles syscon reboot, syscon reboot mode,
> as well as other system control registers (i.e registers for the USB PHY).
>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
> ---
> Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 +
> 1 file changed, 1 insertion(+)
I don't understand why did you send SoC patch to clock. I asked to split
by subsystem.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-19 8:07 ` Krzysztof Kozlowski
@ 2025-02-19 8:10 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-19 8:10 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On Wed, Feb 19, 2025 at 09:07:17AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Feb 19, 2025 at 12:20:28AM +0530, Kaustabh Chakraborty wrote:
> > Add unique identifiers for exynos7870 clocks for every bank. It adds all
> > clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
> > CMU_PERI.
> >
> > Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
> > ---
> > include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++++++++++
> > 1 file changed, 324 insertions(+)
>
> Again, you keep repeating some old patterns ignoring what was added
> recently. This must match compatible, so missing vendor prefix.
>
> Also squash the patch with the binding itself so you will see the
> difference in names.
Let's unify everything to:
samsung,exynos7870-cmu.h
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: clock: document exynos7870 clock driver CMU bindings
2025-02-19 8:05 ` Krzysztof Kozlowski
@ 2025-02-19 8:10 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-19 8:10 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On Wed, Feb 19, 2025 at 09:05:55AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Feb 19, 2025 at 12:20:29AM +0530, Kaustabh Chakraborty wrote:
> > + Exynos7870 clock controller is comprised of several CMU units, generating
> > + clocks for different domains. Those CMU units are modeled as separate device
> > + tree nodes, and might depend on each other. The root clock in that root tree
> > + is an external clock: OSCCLK (26 MHz). This external clock must be defined
> > + as a fixed-rate clock in dts.
> > +
> > + Each clock is assigned an identifier and client nodes can use this identifier
> > + to specify the clock which they consume. All clocks available for usage
> > + in clock consumer nodes are defined as preprocessor macros in
> > + 'dt-bindings/clock/exynos7870.h' header.
>
> Full path and drop quotes
And this filename becames:
samsung,exynos7870-cmu.yaml
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support
2025-02-18 18:50 ` [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support Kaustabh Chakraborty
@ 2025-02-19 8:11 ` Krzysztof Kozlowski
2025-02-24 17:47 ` Kaustabh Chakraborty
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-19 8:11 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On Wed, Feb 19, 2025 at 12:20:32AM +0530, Kaustabh Chakraborty wrote:
> Exynos7870's CLKOUT registers are the same as Exynos5's. Add the PMU
> compatible to the existing CLKOUT ID list.
>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
> ---
> drivers/clk/samsung/clk-exynos-clkout.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
> index 2ef5748c139b37ca5429b9071ee0e06f44fcf28e..9a31b1c311b45096f1d680b6724571854c08725c 100644
> --- a/drivers/clk/samsung/clk-exynos-clkout.c
> +++ b/drivers/clk/samsung/clk-exynos-clkout.c
> @@ -75,6 +75,9 @@ static const struct of_device_id exynos_clkout_ids[] = {
> }, {
> .compatible = "samsung,exynos5433-pmu",
> .data = &exynos_clkout_exynos5,
> + }, {
> + .compatible = "samsung,exynos7870-pmu",
> + .data = &exynos_clkout_exynos5,
I wonder why do we need to keep growing this list? All devices are
compatible, aren't they?
Do you use clkout, BTW?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 3/5] dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible
2025-02-19 8:09 ` Krzysztof Kozlowski
@ 2025-02-19 8:18 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-19 8:18 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On 19/02/2025 09:09, Krzysztof Kozlowski wrote:
> On Wed, Feb 19, 2025 at 12:20:30AM +0530, Kaustabh Chakraborty wrote:
>> Document the compatible string for the Exynos7870 PMU. It's compatible
>> with the Exynos7 PMU design. It handles syscon reboot, syscon reboot mode,
>> as well as other system control registers (i.e registers for the USB PHY).
>>
>> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
>> ---
>> Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>
> I don't understand why did you send SoC patch to clock. I asked to split
> by subsystem.
I guess because of clkout driver. I don't want to grow the clkout OF
device ID table with compatible entries, but I also have doubts that it
is compatible and that you actually tested it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU
2025-02-18 18:50 ` [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU Kaustabh Chakraborty
2025-02-19 8:07 ` Krzysztof Kozlowski
@ 2025-02-23 9:57 ` Krzysztof Kozlowski
1 sibling, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-23 9:57 UTC (permalink / raw)
To: Kaustabh Chakraborty, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On 18/02/2025 19:50, Kaustabh Chakraborty wrote:
> Add unique identifiers for exynos7870 clocks for every bank. It adds all
> clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
> CMU_PERI.
>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
> ---
> include/dt-bindings/clock/exynos7870.h | 324 +++++++++++++++++++++++++++++++++
Filename matching compatible. Look at other latest submissions.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support
2025-02-19 8:11 ` Krzysztof Kozlowski
@ 2025-02-24 17:47 ` Kaustabh Chakraborty
2025-02-24 19:13 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-24 17:47 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, Kaustabh Chakraborty
On 2025-02-19 13:41, Krzysztof Kozlowski wrote:
> On Wed, Feb 19, 2025 at 12:20:32AM +0530, Kaustabh Chakraborty wrote:
>> Exynos7870's CLKOUT registers are the same as Exynos5's. Add the PMU
>> compatible to the existing CLKOUT ID list.
>>
>> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
>> ---
>> drivers/clk/samsung/clk-exynos-clkout.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
>> index 2ef5748c139b37ca5429b9071ee0e06f44fcf28e..9a31b1c311b45096f1d680b6724571854c08725c 100644
>> --- a/drivers/clk/samsung/clk-exynos-clkout.c
>> +++ b/drivers/clk/samsung/clk-exynos-clkout.c
>> @@ -75,6 +75,9 @@ static const struct of_device_id exynos_clkout_ids[] = {
>> }, {
>> .compatible = "samsung,exynos5433-pmu",
>> .data = &exynos_clkout_exynos5,
>> + }, {
>> + .compatible = "samsung,exynos7870-pmu",
>> + .data = &exynos_clkout_exynos5,
>
> I wonder why do we need to keep growing this list? All devices are
> compatible, aren't they?
Well, there are two variants of compatibility having different mask
values.
> Do you use clkout, BTW?
Using the clocks defined by clkout? No. I added it as downstream
had it too. And the devices work fine without it. If you want me
to remove this patch and send the PMU patch to its respective
series I'll do that then (unless you object or suggest something
else).
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support
2025-02-24 17:47 ` Kaustabh Chakraborty
@ 2025-02-24 19:13 ` Krzysztof Kozlowski
2025-02-25 18:33 ` Kaustabh Chakraborty
2025-02-28 19:07 ` David Virag
0 siblings, 2 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-24 19:13 UTC (permalink / raw)
To: Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On 24/02/2025 18:47, Kaustabh Chakraborty wrote:
>>
>> I wonder why do we need to keep growing this list? All devices are
>> compatible, aren't they?
>
> Well, there are two variants of compatibility having different mask
> values.
>
>> Do you use clkout, BTW?
>
> Using the clocks defined by clkout? No. I added it as downstream
> had it too. And the devices work fine without it. If you want me
> to remove this patch and send the PMU patch to its respective
> series I'll do that then (unless you object or suggest something
> else).
clkout is a testing tool and I doubt you can use it on a phone - finding
the actual clkout pins to connect the oscilloscope is tricky.
If this is about to grow and be used, then we should fix the
compatibility and do not duplicate the ID table.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support
2025-02-24 19:13 ` Krzysztof Kozlowski
@ 2025-02-25 18:33 ` Kaustabh Chakraborty
2025-02-28 19:07 ` David Virag
1 sibling, 0 replies; 18+ messages in thread
From: Kaustabh Chakraborty @ 2025-02-25 18:33 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, Kaustabh Chakraborty
On 2025-02-25 00:43, Krzysztof Kozlowski wrote:
>>> Do you use clkout, BTW?
>>
>> Using the clocks defined by clkout? No. I added it as downstream
>> had it too. And the devices work fine without it. If you want me
>> to remove this patch and send the PMU patch to its respective
>> series I'll do that then (unless you object or suggest something
>> else).
>
> clkout is a testing tool and I doubt you can use it on a phone - finding
> the actual clkout pins to connect the oscilloscope is tricky.
Ah, then it's of no apparent use. I guess it'd be better to remove it
now. If required, it can be added back later.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support
2025-02-24 19:13 ` Krzysztof Kozlowski
2025-02-25 18:33 ` Kaustabh Chakraborty
@ 2025-02-28 19:07 ` David Virag
1 sibling, 0 replies; 18+ messages in thread
From: David Virag @ 2025-02-28 19:07 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kaustabh Chakraborty
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette,
Stephen Boyd, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel
On Mon, 2025-02-24 at 20:13 +0100, Krzysztof Kozlowski wrote:
> On 24/02/2025 18:47, Kaustabh Chakraborty wrote:
> > >
> > > I wonder why do we need to keep growing this list? All devices
> > > are
> > > compatible, aren't they?
> >
> > Well, there are two variants of compatibility having different mask
> > values.
> >
> > > Do you use clkout, BTW?
> >
> > Using the clocks defined by clkout? No. I added it as downstream
> > had it too. And the devices work fine without it. If you want me
> > to remove this patch and send the PMU patch to its respective
> > series I'll do that then (unless you object or suggest something
> > else).
>
> clkout is a testing tool and I doubt you can use it on a phone -
> finding
> the actual clkout pins to connect the oscilloscope is tricky.
Actually, jackpotlte uses one of the clkout pins (7885 has two) to feed
it's NFC chip with a clock.
Not sure if any 7870 (or any other Exynos) devices use it for something
similar but here we have at least one example of a non-debug use for
it. I will avoid it on 7885 though until it's actually needed and I can
test the functionality (and when I have the time to work on 7885
again).
Best Regards,
David
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2025-02-28 19:12 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-18 18:50 [PATCH v3 0/5] Introduce support for Exynos7870 clocks and PMU Kaustabh Chakraborty
2025-02-18 18:50 ` [PATCH v3 1/5] dt-bindings: clock: add clock definitions for exynos7870 CMU Kaustabh Chakraborty
2025-02-19 8:07 ` Krzysztof Kozlowski
2025-02-19 8:10 ` Krzysztof Kozlowski
2025-02-23 9:57 ` Krzysztof Kozlowski
2025-02-18 18:50 ` [PATCH v3 2/5] dt-bindings: clock: document exynos7870 clock driver CMU bindings Kaustabh Chakraborty
2025-02-19 8:05 ` Krzysztof Kozlowski
2025-02-19 8:10 ` Krzysztof Kozlowski
2025-02-18 18:50 ` [PATCH v3 3/5] dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible Kaustabh Chakraborty
2025-02-19 8:09 ` Krzysztof Kozlowski
2025-02-19 8:18 ` Krzysztof Kozlowski
2025-02-18 18:50 ` [PATCH v3 4/5] clk: samsung: add initial exynos7870 clock driver Kaustabh Chakraborty
2025-02-18 18:50 ` [PATCH v3 5/5] clk: samsung: add exynos7870 CLKOUT support Kaustabh Chakraborty
2025-02-19 8:11 ` Krzysztof Kozlowski
2025-02-24 17:47 ` Kaustabh Chakraborty
2025-02-24 19:13 ` Krzysztof Kozlowski
2025-02-25 18:33 ` Kaustabh Chakraborty
2025-02-28 19:07 ` David Virag
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