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Tue, 27 Oct 2020 16:21:36 +0000 MIME-Version: 1.0 Date: Tue, 27 Oct 2020 16:21:36 +0000 From: Marc Zyngier To: Mark Rutland Subject: Re: [PATCH 07/11] KVM: arm64: Inject AArch64 exceptions from HYP In-Reply-To: <20201026142201.GH12454@C02TD0UTHF1T.local> References: <20201026133450.73304-1-maz@kernel.org> <20201026133450.73304-8-maz@kernel.org> <20201026142201.GH12454@C02TD0UTHF1T.local> User-Agent: Roundcube Webmail/1.4.9 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kernel-team@android.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_122139_835177_E689A156 X-CRM114-Status: GOOD ( 20.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-10-26 14:22, Mark Rutland wrote: > On Mon, Oct 26, 2020 at 01:34:46PM +0000, Marc Zyngier wrote: >> Move the AArch64 exception injection code from EL1 to HYP, leaving >> only the ESR_EL1 updates to EL1. In order to come with the differences >> between VHE and nVHE, two set of system register accessors are >> provided. >> >> SPSR, ELR, PC and PSTATE are now completely handled in the hypervisor. >> >> Signed-off-by: Marc Zyngier > >> void kvm_inject_exception(struct kvm_vcpu *vcpu) >> { >> + switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) { >> + case KVM_ARM64_EXCEPT_AA64_EL1_SYNC: >> + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync); >> + break; >> + case KVM_ARM64_EXCEPT_AA64_EL1_IRQ: >> + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_irq); >> + break; >> + case KVM_ARM64_EXCEPT_AA64_EL1_FIQ: >> + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_fiq); >> + break; >> + case KVM_ARM64_EXCEPT_AA64_EL1_SERR: >> + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_serror); >> + break; >> + default: >> + /* EL2 are unimplemented until we get NV. One day. */ >> + break; >> + } >> } > > Huh, we're going to allow EL1 to inject IRQ/FIQ/SERROR *exceptions* > directly, rather than pending those via HCR_EL2.{VI,VF,VSE}? We never > used to have code to do that. True, and I feel like I got carried away while thinking of NV. Though James had some "interesting" use case [1] lately... > If we're going to support that we'll need to check against the DAIF > bits > to make sure we don't inject an exception that can't be architecturally > taken. Nah, forget it. Unless we really need to implement something like James' idea, I'd rather drop this altogether. > I guess we'll tighten that up along with the synchronous exception > checks, but given those three cases aren't needed today it might be > worth removing them from the switch for now and/or adding a comment to > that effect. Agreed. M. [1] https://lore.kernel.org/r/20201023165108.15061-1-james.morse@arm.com -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel