From: Marc Zyngier <maz@kernel.org>
To: Auger Eric <eric.auger@redhat.com>
Cc: kvm@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
linux-arm-kernel@lists.infradead.org, kernel-team@android.com,
kvmarm@lists.cs.columbia.edu,
Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: Re: [PATCH] KVM: arm64: Allow in-atomic injection of SPIs
Date: Mon, 08 Jun 2020 18:19:05 +0100 [thread overview]
Message-ID: <e3a8ea9947616f895021310127fe1477@kernel.org> (raw)
In-Reply-To: <0a3875f0-9918-51f3-08eb-29a72eeb1306@redhat.com>
Hi Eric,
On 2020-06-08 17:58, Auger Eric wrote:
> Hi Marc,
>
> On 5/26/20 6:11 PM, Marc Zyngier wrote:
>> On a system that uses SPIs to implement MSIs (as it would be
>> the case on a GICv2 system exposing a GICv2m to its guests),
>> we deny the possibility of injecting SPIs on the in-atomic
>> fast-path.
>>
>> This results in a very large amount of context-switches
>> (roughly equivalent to twice the interrupt rate) on the host,
>> and suboptimal performance for the guest (as measured with
>> a test workload involving a virtio interface backed by vhost-net).
>> Given that GICv2 systems are usually on the low-end of the spectrum
>> performance wise, they could do without the aggravation.
>>
>> We solved this for GICv3+ITS by having a translation cache. But
>> SPIs do not need any extra infrastructure, and can be immediately
>> injected in the virtual distributor as the locking is already
>> heavy enough that we don't need to worry about anything.
>>
>> This halves the number of context switches for the same workload.
>>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>> ---
>> arch/arm64/kvm/vgic/vgic-irqfd.c | 20 ++++++++++++++++----
>> arch/arm64/kvm/vgic/vgic-its.c | 3 +--
>> 2 files changed, 17 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/vgic/vgic-irqfd.c
>> b/arch/arm64/kvm/vgic/vgic-irqfd.c
>> index d8cdfea5cc96..11a9f81115ab 100644
>> --- a/arch/arm64/kvm/vgic/vgic-irqfd.c
>> +++ b/arch/arm64/kvm/vgic/vgic-irqfd.c
> There is still a comment above saying
> * Currently only direct MSI injection is supported.
I believe this comment to be correct. There is no path other
than MSI injection that leads us here. Case in point, we only
ever inject a rising edge through this API, never a falling one.
>> @@ -107,15 +107,27 @@ int kvm_arch_set_irq_inatomic(struct
>> kvm_kernel_irq_routing_entry *e,
>> struct kvm *kvm, int irq_source_id, int level,
>> bool line_status)
>> {
>> - if (e->type == KVM_IRQ_ROUTING_MSI && vgic_has_its(kvm) && level) {
>> + if (!level)
>> + return -EWOULDBLOCK;
>> +
>> + switch (e->type) {
>> + case KVM_IRQ_ROUTING_MSI: {
>> struct kvm_msi msi;
>>
>> + if (!vgic_has_its(kvm))
>> + return -EINVAL;
> Shouldn't we return -EWOULDBLOCK by default?
> QEMU does not use that path with GICv2m but in kvm_set_routing_entry()
> I
> don't see any check related to the ITS.
Fair enough. I really don't anticipate anyone to be using
KVM_IRQ_ROUTING_MSI with anything but the ITS, but who knows,
people are crazy! ;-)
>> +
>> kvm_populate_msi(e, &msi);
>> - if (!vgic_its_inject_cached_translation(kvm, &msi))
>> - return 0;
>> + return vgic_its_inject_cached_translation(kvm, &msi);
>
>> }
>>
>> - return -EWOULDBLOCK;
>> + case KVM_IRQ_ROUTING_IRQCHIP:
>> + /* Injecting SPIs is always possible in atomic context */
>> + return vgic_irqfd_set_irq(e, kvm, irq_source_id, 1, line_status);
> what about the mutex_lock(&kvm->lock) called from within
> vgic_irqfd_set_irq/kvm_vgic_inject_irq/vgic_lazy_init
Holy crap. The lazy GIC init strikes again :-(.
How about this on top of the existing patch:
diff --git a/arch/arm64/kvm/vgic/vgic-irqfd.c
b/arch/arm64/kvm/vgic/vgic-irqfd.c
index 11a9f81115ab..6e5ca04d5589 100644
--- a/arch/arm64/kvm/vgic/vgic-irqfd.c
+++ b/arch/arm64/kvm/vgic/vgic-irqfd.c
@@ -115,19 +115,23 @@ int kvm_arch_set_irq_inatomic(struct
kvm_kernel_irq_routing_entry *e,
struct kvm_msi msi;
if (!vgic_has_its(kvm))
- return -EINVAL;
+ break;
kvm_populate_msi(e, &msi);
return vgic_its_inject_cached_translation(kvm, &msi);
}
case KVM_IRQ_ROUTING_IRQCHIP:
- /* Injecting SPIs is always possible in atomic context */
+ /*
+ * Injecting SPIs is always possible in atomic context
+ * as long as the damn vgic is initialized.
+ */
+ if (unlikely(!vgic_initialized(kvm)))
+ break;
return vgic_irqfd_set_irq(e, kvm, irq_source_id, 1, line_status);
-
- default:
- return -EWOULDBLOCK;
}
+
+ return -EWOULDBLOCK;
}
int kvm_vgic_setup_default_irq_routing(struct kvm *kvm)
Thanks,
M.
--
Jazz is not dead. It just smells funny...
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-08 17:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-26 16:11 [PATCH] KVM: arm64: Allow in-atomic injection of SPIs Marc Zyngier
2020-05-27 7:41 ` Zenghui Yu
2020-05-27 7:55 ` Marc Zyngier
2020-05-27 8:42 ` Zenghui Yu
2020-06-08 16:58 ` Auger Eric
2020-06-08 17:19 ` Marc Zyngier [this message]
2020-06-09 7:48 ` Auger Eric
2020-06-09 8:21 ` Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e3a8ea9947616f895021310127fe1477@kernel.org \
--to=maz@kernel.org \
--cc=eric.auger@redhat.com \
--cc=james.morse@arm.com \
--cc=julien.thierry.kdev@gmail.com \
--cc=kernel-team@android.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=suzuki.poulose@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).