From: Michal Simek <michal.simek@amd.com>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>,
Michael Grzeschik <m.grzeschik@pengutronix.de>,
<linux-arm-kernel@lists.infradead.org>
Cc: <kernel@pengutronix.de>, <robh+dt@kernel.org>,
<michal.simek@xilinx.com>, <krzysztof.kozlowski+dt@linaro.org>
Subject: Re: Meaning of commented out dma-coherent in ZynqMP DWC3 DT node (Was: Re: [PATCH] arm64: zynqmp: Enable hs termination flag for USB dwc3 controller)
Date: Wed, 30 Nov 2022 18:17:53 +0100 [thread overview]
Message-ID: <e3fdbab4-5b9e-d80e-88eb-aa7811d9ef91@amd.com> (raw)
In-Reply-To: <36f3970c-9f3e-a0f4-5810-f93ea8223e74@pengutronix.de>
Hi,
On 11/30/22 18:12, Ahmad Fatoum wrote:
> Hello,
>
> On 30.11.22 18:08, Michal Simek wrote:
>> Hi,
>>
>> On 11/30/22 18:02, Ahmad Fatoum wrote:
>>> Hello!
>>>
>>> On 23.10.22 23:56, Michael Grzeschik wrote:
>>>> Since we need to support legacy phys with the dwc3 controller,
>>>> we enable this quirk on the zynqmp platforms.
>>>
>>> Slightly off-topic question below.
>>>
>>>>
>>>> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
>>>> ---
>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++
>>>> 1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> index a549265e55f6e7..7c1af75f33a05b 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> @@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 {
>>>> clock-names = "bus_early", "ref";
>>>> iommus = <&smmu 0x860>;
>>>> snps,quirk-frame-length-adjustment = <0x20>;
>>>> + snps,resume-hs-terminations;
>>>> /* dma-coherent; */
>>>
>>> Is it possible to configure coherent DMA for the device and this is currently
>>> not done or how should this comment be interpreted?
>>
>>
>> I didn't try it for a while but before you start a53 you can enable CCI and then dma-coherent flags should be enabled.
>
> I see. Wouldn't this apply to all DMA-capable devices then? So this comment would be better
> placed top-level in /soc?
yes of course.
>
> Also, why did you decide against having cache coherency be the default?
> I'd expect this to be a performance improvement (if it functions correctly).
I haven't seen such a request to enable it by default but from build perspective
you need to do one more additional step which none is really doing. Definitely
there is missing code in bootloader which is also sharing the same DT description.
I know that we were trying that configuration in past but not sure if this is in
regression or if there is any issue with any driver.
Thanks,
Michal
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prev parent reply other threads:[~2022-11-30 17:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-23 21:56 [PATCH] arm64: zynqmp: Enable hs termination flag for USB dwc3 controller Michael Grzeschik
2022-11-14 15:57 ` Michael Grzeschik
2022-11-30 16:57 ` Michal Simek
2022-11-30 17:02 ` Meaning of commented out dma-coherent in ZynqMP DWC3 DT node (Was: Re: [PATCH] arm64: zynqmp: Enable hs termination flag for USB dwc3 controller) Ahmad Fatoum
2022-11-30 17:08 ` Michal Simek
2022-11-30 17:12 ` Ahmad Fatoum
2022-11-30 17:17 ` Michal Simek [this message]
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