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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-845a3fedaefsm11603061b3a.23.2026.06.28.20.48.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Jun 2026 20:48:53 -0700 (PDT) Message-ID: Date: Mon, 29 Jun 2026 11:48:49 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 4/7] drm/verisilicon: make axi and ahb clocks optional To: Icenowy Zheng , maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260625094449.708386-1-a0987203069@gmail.com> <20260625094449.708386-5-a0987203069@gmail.com> Content-Language: en-US From: Joey Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260628_204854_691879_00DBF0C4 X-CRM114-Status: GOOD ( 16.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/26/2026 4:03 PM, Icenowy Zheng wrote: > 在 2026-06-25四的 17:44 +0800，Joey Lu写道： >> The Nuvoton MA35D1 SoC integrates a DCUltraLite display controller >> whose >> AXI and AHB bus clocks share a single gate enable bit with the >> display >> core clock, so the clock driver does not expose them separately. This >> patch makes the axi and ahb clocks optional in the probe. >> >> Signed-off-by: Joey Lu > ``` > Reviewed-by: Icenowy Zheng > ``` > > Thanks, > Icenowy Thank you for the review. I will revert this patch entirely. As discussed in the binding review, axi and ahb clocks will now always be supplied in the devicetree using the same phandle as the core clock gate, so making them optional in the driver is no longer needed. >> --- >>  drivers/gpu/drm/verisilicon/vs_dc.c | 4 ++-- >>  1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c >> b/drivers/gpu/drm/verisilicon/vs_dc.c >> index 9729b693d360..fd1f5fe67a68 100644 >> --- a/drivers/gpu/drm/verisilicon/vs_dc.c >> +++ b/drivers/gpu/drm/verisilicon/vs_dc.c >> @@ -90,13 +90,13 @@ static int vs_dc_probe(struct platform_device >> *pdev) >>   return PTR_ERR(dc->core_clk); >>   } >> >> - dc->axi_clk = devm_clk_get_enabled(dev, "axi"); >> + dc->axi_clk = devm_clk_get_optional_enabled(dev, "axi"); >>   if (IS_ERR(dc->axi_clk)) { >>   dev_err(dev, "can't get axi clock\n"); >>   return PTR_ERR(dc->axi_clk); >>   } >> >> - dc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); >> + dc->ahb_clk = devm_clk_get_optional_enabled(dev, "ahb"); >>   if (IS_ERR(dc->ahb_clk)) { >>   dev_err(dev, "can't get ahb clock\n"); >>   return PTR_ERR(dc->ahb_clk);