From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35D6FC433EF for ; Tue, 12 Jul 2022 13:39:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cn1xUS4eaHXL1Vr8gNllRXOVFt/2rHyGlVaLCgqxx60=; b=QSyjS/96esWGhH DQ2RTKArzvC3ZmKv/EN+/pSPfkCqdVBVV6c4EQqTcDTRxx3sl3UliAiunI4UgjtsKs/x+WFkaHbyu ibwueuwCs8NWGy4dalhQ60SDshFWUHcTGganPZrl/pxVIXmRjuF0voLHXQSwbfEuR43hAs10CEl7c om8h6ETelkM7lFt7ZfykPablLA340HH0rer0iaKLeVNyuELNTdrLgJMYQvJ6Kwa+0lFBVsQpDY/WY DnkTi9SC2VwQ3nEiiCIGKQZAy/AEDH3iDNrK8Q/an7uxpU3p6x3BLVaauvvvQwBWFIfzBaKq9HsZX EJlBHwwcsIT5gFPSzXqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBG5Q-00BPuA-Rw; Tue, 12 Jul 2022 13:38:01 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBG5M-00BPrA-9G for linux-arm-kernel@lists.infradead.org; Tue, 12 Jul 2022 13:37:58 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26C9Fa5x002441; Tue, 12 Jul 2022 15:37:45 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=h4xD17V7DTR/YNErBVRjs3G7RJZlt2Jn4LyRZD6px+4=; b=FJAxMZeSr66ZY5WN87Yvn3qR9Bemn1VfFdpQ5//MFtocWtSe/WNGaytc90QqANxrAOmV sVNWVMUxdB0Qp3jJtUYNOaRtnzjlLv2XEsfQpqJi6ahJ5RcZmfLewH9GhOvz8Tvv4PDW FRXQQ9z/REk2wuTE60sKbb1YQrJ3t5YIXIg/Xvr3O1yFYbOCn9rCebilXSMTKT2yq909 sCmudFgylUs+nXKUme55+ptXcb9LliRuGoTgNcp2IFT/BBwb3uBtdtwq6z8Izc0Vhk3E hvljL3gcXV617KkptqhybuOqqKw7eanAvWgvjJD0Y98xpTaF5Gr17xDtmFYnR1wZQXKB 5w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3h9173k3qb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Jul 2022 15:37:45 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 30356100034; Tue, 12 Jul 2022 15:37:44 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2179321FEBB; Tue, 12 Jul 2022 15:37:44 +0200 (CEST) Received: from [10.211.14.207] (10.75.127.45) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Tue, 12 Jul 2022 15:37:42 +0200 Message-ID: Date: Tue, 12 Jul 2022 15:37:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 1/4] docs: arm: stm32: introduce STM32 DMA-MDMA chaining feature Content-Language: en-US To: Jonathan Corbet , Vinod Koul , Maxime Coquelin , Alexandre Torgue CC: , , , , , Marek Vasut References: <20220711084703.268481-1-amelie.delaunay@foss.st.com> <20220711084703.268481-2-amelie.delaunay@foss.st.com> <87a69ffzvk.fsf@meer.lwn.net> From: Amelie Delaunay In-Reply-To: <87a69ffzvk.fsf@meer.lwn.net> X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-12_08,2022-07-12_01,2022-06-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220712_063756_842631_448CAD7B X-CRM114-Status: GOOD ( 29.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/11/22 17:11, Jonathan Corbet wrote: > Amelie Delaunay writes: > >> STM32 DMA-MDMA chaining feature is available on STM32 SoCs which embed >> STM32 DMAMUX, DMA and MDMA controllers. It is the case on STM32MP1 SoCs but >> also on STM32H7 SoCs. But focus is on STM32MP1 SoCs, using DDR. >> This documentation aims to explain how to use STM32 DMA-MDMA chaining >> feature in drivers of STM32 peripheral having request lines on STM32 DMA. >> >> Signed-off-by: Amelie Delaunay >> --- >> .../arm/stm32/stm32-dma-mdma-chaining.rst | 365 ++++++++++++++++++ >> 1 file changed, 365 insertions(+) >> create mode 100644 Documentation/arm/stm32/stm32-dma-mdma-chaining.rst > > When you add a new RST file you also need to add it to index.rst > somewhere so that it becomes part of the docs build. > Thanks for you review. I'll add it to index.rst, with other stm32 documentations. >> diff --git a/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst b/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst >> new file mode 100644 >> index 000000000000..bfbbadc45aa7 >> --- /dev/null >> +++ b/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst >> @@ -0,0 +1,365 @@ >> +.. SPDX-License-Identifier: GPL-2.0 >> + >> +======================= >> +STM32 DMA-MDMA chaining >> +======================= >> + >> + >> +Introduction >> +------------ >> + >> + This document describes the STM32 DMA-MDMA chaining feature. But before going further, let's >> + introduce the peripherals involved. > > Please keep to the 80-column limit for documentation, it makes it easier > to read. > OK, I prepare a v2 with a 80-column limit for the documentation patch. >> + To offload data transfers from the CPU, STM32 microprocessors (MPUs) embed direct memory access >> + controllers (DMA). >> + >> + STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA request routing >> + capabilities are enhanced by a DMA request multiplexer (STM32 DMAMUX). >> + >> + **STM32 DMAMUX** >> + >> + STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA controller (STM32MP1 >> + counts two STM32 DMA controllers) channels. >> + >> + **STM32 DMA** >> + >> + STM32 DMA is mainly used to implement central data buffer storage (usually in the system SRAM) for >> + different peripheral. It can access external RAMs but without the ability to generate convenient >> + burst transfer ensuring the best load of the AXI. >> + >> + **STM32 MDMA** >> + >> + STM32 MDMA (Master DMA) is mainly used to manage direct data transfers between RAM data buffers >> + without CPU intervention. It can also be used in a hierarchical structure that uses STM32 DMA as >> + first level data buffer interfaces for AHB peripherals, while the STM32 MDMA acts as a second >> + level DMA with better performance. As a AXI/AHB master, STM32 MDMA can take control of the AXI/AHB >> + bus. >> + >> + >> +Principles >> +---------- >> + >> + STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and STM32 MDMA controllers. >> + >> + STM32 DMA has a circular Double Buffer Mode (DBM). At each end of transaction (when DMA data >> + counter - DMA_SxNDTR - reaches 0), the memory pointers (configured with DMA_SxSM0AR and >> + DMA_SxM1AR) are swapped and the DMA data counter is automatically reloaded. This allows the SW or >> + the STM32 MDMA to process one memory area while the second memory area is being filled/used by the >> + STM32 DMA transfer. >> + >> + With STM32 MDMA linked-list mode, a single request initiates the data array (collection of nodes) >> + to be transferred until the linked-list pointer for the channel is null. The channel transfer >> + complete of the last node is the end of transfer, unless first and last nodes are linked to each >> + other, in such a case, the linked-list loops on to create a circular MDMA transfer. >> + >> + STM32 MDMA has direct connections with STM32 DMA. This enables autonomous communication and >> + synchronization between peripherals, thus saving CPU resources and bus congestion. Transfer >> + Complete signal of STM32 DMA channel can triggers STM32 MDMA transfer. STM32 MDMA can clear the >> + request generated by the STM32 DMA by writing to its Interrupt Clear register (whose address is >> + stored in MDMA_CxMAR, and bit mask in MDMA_CxMDR). >> + >> + .. csv-table:: STM32 MDMA interconnect table with STM32 DMA >> + :header: "STM32 DMAMUX channels", "STM32 DMA controllers channels", >> + "STM32 DMA Transfer Complete signal", "STM32 MDMA request" > > If at all possible, please use simple tables; that makes the plain text > documentation much easier to read. > It is possible, with some extra lines. I'll update it in v2 coming soon. > [...] > > Thanks, > > jon Regards, Amelie _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel