From: Krzysztof Kozlowski <krzk@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>,
Yushan Wang <wangyushan12@huawei.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Drew Fustini <fustini@kernel.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Linus Walleij <linus.walleij@linaro.org>,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: fanghao11@huawei.com, linuxarm@huawei.com,
liuyonglong@huawei.com, prime.zeng@hisilicon.com,
Zhou Wang <wangzhou1@hisilicon.com>,
Wei Xu <xuwei5@hisilicon.com>
Subject: Re: [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC
Date: Thu, 5 Feb 2026 10:37:11 +0100 [thread overview]
Message-ID: <e59c7556-d001-4a34-8db3-127dc25f3897@kernel.org> (raw)
In-Reply-To: <a8ba1c0b-e7c8-44c5-b785-42752f7f5d8f@app.fastmail.com>
On 03/02/2026 18:19, Arnd Bergmann wrote:
> On Tue, Feb 3, 2026, at 17:18, Yushan Wang wrote:
>> The driver will create a file of `/dev/hisi_l3c` on init, mmap
>> operations to it will allocate a memory region that is guaranteed to be
>> placed in L3 cache.
>>
>> The driver also provides unmap() to deallocated the locked memory.
>>
>> The driver also provides an ioctl interface for user to get cache lock
>> information, such as lock restrictions and locked sizes.
>>
>> Signed-off-by: Yushan Wang <wangyushan12@huawei.com>
>
> Hi Yushan,
>
> Thanks for your submission. Since we are in the last week of
> the merge window, this is not going to be linux-7.0 material,
> but I'll have a quick look for now.
To be clear - this is a v3 but with removed previous history...
Previous version:
https://lore.kernel.org/all/20251217102357.1730573-2-wangyushan12@huawei.com/
Or even v4?
https://lore.kernel.org/all/20250122065803.3363926-2-wangyushan12@huawei.com/
Yushan, please start versioning your patches correctly. Use b4 or git
format-patch -vx
Otherwise, please explain us how can we compare it with `b4 diff` with
previous version?
Sending something AGAIN as v1 ignoring entire previous submission is
clear no go. Like you are trying till it succeeds. Negative review?
Let's try from v1 this time...
This is not correct and it should not be my task to find your previous
discussions and decipher this v1.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-02-05 9:37 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-03 16:18 [PATCH 0/3] soc: Enable cache lockdown for HiSilicon L3 cache Yushan Wang
2026-02-03 16:18 ` [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC Yushan Wang
2026-02-03 17:19 ` Arnd Bergmann
2026-02-04 9:51 ` wangyushan
2026-02-05 9:37 ` Krzysztof Kozlowski [this message]
2026-02-05 11:19 ` wangyushan
2026-02-05 11:23 ` Krzysztof Kozlowski
2026-02-05 11:30 ` wangyushan
2026-02-04 0:10 ` Linus Walleij
2026-02-04 9:53 ` wangyushan
2026-02-04 10:06 ` Linus Walleij
2026-02-04 13:40 ` Jonathan Cameron
2026-02-04 13:44 ` Jonathan Cameron
2026-02-05 2:20 ` SeongJae Park
2026-02-05 9:12 ` Linus Walleij
2026-02-05 10:18 ` Jonathan Cameron
2026-02-05 13:47 ` Linus Walleij
2026-02-05 14:38 ` Arnd Bergmann
2026-02-06 8:05 ` Linus Walleij
2026-02-05 14:37 ` Ben Horgan
2026-02-06 9:54 ` wangyushan
2026-02-06 16:15 ` Ben Horgan
2026-02-06 10:07 ` wangyushan
2026-02-06 10:44 ` Arnd Bergmann
2026-02-06 12:44 ` Linus Walleij
2026-02-04 2:47 ` kernel test robot
2026-02-03 16:18 ` [PATCH 2/3] soc cache: L3 cache lockdown support " Yushan Wang
2026-02-03 16:18 ` [PATCH 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache Yushan Wang
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