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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h8oke-0008AH-Du; Tue, 26 Mar 2019 16:16:36 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h8okW-00088f-9D for linux-arm-kernel@lists.infradead.org; Tue, 26 Mar 2019 16:16:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C65AB1596; Tue, 26 Mar 2019 09:16:23 -0700 (PDT) Received: from [10.37.12.89] (unknown [10.37.12.89]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A4AE3F614; Tue, 26 Mar 2019 09:16:21 -0700 (PDT) Subject: Re: [PATCH v2 13/16] coresight: tmc-etr: Allow events to use the same ETR buffer To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org References: <20190325215632.17013-1-mathieu.poirier@linaro.org> <20190325215632.17013-14-mathieu.poirier@linaro.org> From: Suzuki K Poulose Message-ID: Date: Tue, 26 Mar 2019 16:18:35 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20190325215632.17013-14-mathieu.poirier@linaro.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190326_091628_661682_9A504BBC X-CRM114-Status: GOOD ( 17.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, coresight@lists.linaro.org, Mike.Leach@arm.com, leo.yan@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 03/25/2019 09:56 PM, Mathieu Poirier wrote: > This patch uses the pid of the process being traced to aggregate traces > coming from different processors in the same sink, something that is > required when collecting traces in CPU-wide mode when the CoreSight HW > enacts a N:1 source/sink topology. > > Signed-off-by: Mathieu Poirier > --- > .../hwtracing/coresight/coresight-tmc-etr.c | 71 +++++++++++++++++-- > 1 file changed, 65 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index 7254fafdf1c2..cbabf88bd51d 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -41,6 +42,9 @@ struct etr_perf_buffer { > void **pages; > }; > > +static DEFINE_IDR(session_idr); > +static DEFINE_MUTEX(session_idr_lock); Please correct me if I am wrong here. What we now do with this series is - One event per CPU and thus one ETR perf buf per CPU. - One *ETR buf* per PID, from the IDR hash list. However, if we have 1:1 situation, we will have : N (say 2 ETRs), but one *ETR buf* as they all share the same PID, implying multiple multiple ETRs will try to use the same etr buf, which could corrupt the trace data ? Instead, what we need in that situation is : One ETR buf perf PID+ETR device. i.e, etr_bufs must be per ETR. So should the IDR be specific to an ETR ? Or do we not support a session with multiple ETRs involved (1:1) ? Cheers Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel