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Mon, 17 May 2021 11:24:28 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 27C2D10002A; Mon, 17 May 2021 11:24:27 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 12D9A221060; Mon, 17 May 2021 11:24:27 +0200 (CEST) Received: from lmecxl0573.lme.st.com (10.75.127.50) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 17 May 2021 11:24:26 +0200 Subject: Re: [PATCH v2 1/3] spi: spi-mem: add automatic poll status functions To: Boris Brezillon CC: Mark Brown , Miquel Raynal , Vignesh Raghavendra , , Alexandre Torgue , , , , , References: <20210507131756.17028-1-patrice.chotard@foss.st.com> <20210507131756.17028-2-patrice.chotard@foss.st.com> <20210517094140.53cb643a@collabora.com> From: Patrice CHOTARD Message-ID: Date: Mon, 17 May 2021 11:24:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210517094140.53cb643a@collabora.com> Content-Language: en-US X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-17_03:2021-05-12, 2021-05-17 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210517_022434_994695_936BB10C X-CRM114-Status: GOOD ( 28.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Boris On 5/17/21 9:41 AM, Boris Brezillon wrote: > On Fri, 7 May 2021 15:17:54 +0200 > wrote: > >> +/** >> + * spi_mem_poll_status() - Poll memory device status >> + * @mem: SPI memory device >> + * @op: the memory operation to execute >> + * @mask: status bitmask to ckeck >> + * @match: (status & mask) expected value >> + * @timeout_ms: timeout in milliseconds >> + * >> + * This function send a polling status request to the controller driver >> + * >> + * Return: 0 in case of success, -ETIMEDOUT in case of error, >> + * -EOPNOTSUPP if not supported. >> + */ >> +int spi_mem_poll_status(struct spi_mem *mem, >> + const struct spi_mem_op *op, >> + u16 mask, u16 match, u16 timeout_ms) > > Maybe you should pass a delay_us too, to poll the status at the right > rate in the SW-based case (can also be used by drivers if they need to Ok, i will add a polling_rate_us parameter to poll_status() callback, even if in STM32 driver case we will not use it, i agree it should be useful depending of driver's implementation. > configure the polling rate). You could also add an initial_delay_us to > avoid polling the status too early: an erase operation will take longer > than a write which will take longer than a read. No need to check the > status just after issuing the command, especially if the polling is > done in SW. Those 2 arguments should also be passed to the driver. Regarding the addition of an initial_delay_us. We got two solution: - use the same polling rate already used by read_poll_timeout() and set read_poll_timeout()'s sleep_before_read parameter to true (in our case 20 us will be used as initial delay and as polling rate). - add an udelay(initial_delay_us) or even better usleep_range(initial_delay_us, initial_delay_us + delta) before calling read_poll_timeout(). I imagine you prefer the second solution ? By adding polling_rate_us and initial_delay_us parameters to spi_mem_poll_status(), it implies to update all spinand_wait() calls for different operations (reset, read page, write page, erase) with respective initial_delay_us/polling_rate_us values for spi_mem_poll_status()'s parameters. Can you provide adequate initial_delay_us and polling rate_us for each operation type ?. Thanks Patrice > >> +{ >> + struct spi_controller *ctlr = mem->spi->controller; >> + unsigned long ms; >> + int ret = -EOPNOTSUPP; >> + int exec_op_ret; >> + u16 *status; >> + >> + if (!spi_mem_supports_op(mem, op)) >> + return ret; >> + >> + if (ctlr->mem_ops && ctlr->mem_ops->poll_status) { >> + ret = spi_mem_access_start(mem); >> + if (ret) >> + return ret; >> + >> + reinit_completion(&ctlr->xfer_completion); >> + >> + ret = ctlr->mem_ops->poll_status(mem, op, mask, match, >> + timeout_ms); >> + >> + ms = wait_for_completion_timeout(&ctlr->xfer_completion, >> + msecs_to_jiffies(timeout_ms)); >> + >> + spi_mem_access_end(mem); >> + if (!ms) >> + return -ETIMEDOUT; >> + } else { >> + status = (u16 *)op->data.buf.in; >> + ret = read_poll_timeout(spi_mem_exec_op, exec_op_ret, >> + ((*status) & mask) == match, 20, >> + timeout_ms * 1000, false, mem, op); >> + if (exec_op_ret) >> + return exec_op_ret; >> + } >> + >> + return ret; >> +} >> +EXPORT_SYMBOL_GPL(spi_mem_poll_status); >> + _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel