[PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Alexander Sverdlin]

This series adds very basic support for Milk-V Duo Module 01 EVB [1] in
arm64 mode. The SoC (SG2000) is dual-arch, RiscV and ARM64, the latter has
been chosen because the upstream toolchain can be utilized.

Sophgo SG2000 seems to be a continuation of the Cvitek CV18xx series, same
peripherals with an addition of ARM64 core. Therefore it would be
beneficial not to copy-paste the peripherals' device-tree, but rather split
the most suitable riscv DT into ARCH-specific and peripherals parts and
just include the latter on the arm64 side.

This series adds the device-tree for Milk-V Duo Module 01 EVB, which
in turn contains Milk-V Duo Module 01 (separate .dtsi) on it, which has
SG2000 SoC inside (separate .dtsi).

This series has been tested with Sophgo-provided U-Boot binary [2]: it
boots from SD card, pinctrl, serial, GPIO drivers are functional (same
as for RiscV-based CV18xx SoCs).
New reset driver is provided as an alternative to the ATF PSCI handler,
which Sophgo only provides in binary form.

Partial SoC documentation is available [3].

This series lacks the support of:
- USB
- Audio
- Ethernet
- WiFi
- Bluetooth
- eMMC
- Video

It would probably make sense that the whole series would go into SOC tree,
even though technically nothing prevents the reboot/reset driver to come
in PM/reset tree. If everything would come together, `reboot` command would
work out of the box.

[1] https://milkv.io/docs/duo/getting-started/duo-module-01
[2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
[3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf

Alexander Sverdlin (10):
  arm64: Add SOPHGO SOC family Kconfig support
  riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts
  arm64: dts: sophgo: Add initial SG2000 SoC device tree
  arm64: dts: sophgo: Add Duo Module 01
  arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
  dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl
    compatible
  dt-bindings: reset: sophgo: Add CV18xx reset controller
  riscv/arm64: dts: cv18xx: Add sysctl and reset nodes
  power: reset: cv18xx: New driver
  arm64: defconfig: Enable rudimentary Sophgo SG2000 support

 .../devicetree/bindings/mfd/syscon.yaml       |   4 +
 .../bindings/reset/sophgo,cv1800-reset.yaml   |  38 ++
 MAINTAINERS                                   |   1 +
 arch/arm64/Kconfig.platforms                  |  12 +
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/sophgo/Makefile           |   2 +
 arch/arm64/boot/dts/sophgo/sg2000.dtsi        |  79 +++++
 .../sophgo/sg2000_milkv_duo_module_01.dtsi    |  84 +++++
 .../sophgo/sg2000_milkv_duo_module_01_evb.dts |  30 ++
 arch/arm64/configs/defconfig                  |   3 +
 arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 329 ++++++++++++++++++
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +---------------
 drivers/power/reset/Kconfig                   |  12 +
 drivers/power/reset/Makefile                  |   1 +
 drivers/power/reset/cv18xx-reset.c            |  89 +++++
 16 files changed, 689 insertions(+), 303 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
 create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
 create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
 create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
 create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
 create mode 100644 drivers/power/reset/cv18xx-reset.c

-- 
2.48.1

[PATCH 01/10] arm64: Add SOPHGO SOC family Kconfig support

[Alexander Sverdlin]

First user will be Aarch64 core within SG2000 SoC.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 arch/arm64/Kconfig.platforms | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 02f9248f7c84..f45f3f05edf8 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -307,6 +307,18 @@ config ARCH_INTEL_SOCFPGA
 	  Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
 	  Agilex and eASIC N5X.
 
+config ARCH_SOPHGO
+	bool "Sophgo SoCs"
+	select CLK_SOPHGO_CV1800
+	select MFD_SYSCON
+	select RESET_CONTROLLER
+	help
+	  This enables support for Sophgo SoC platform hardware, such as
+	  SG2000.
+
+	  Enable this option if you are going to boot your dual-ARCH SoC in
+	  ARM64 mode.
+
 config ARCH_STM32
 	bool "STMicroelectronics STM32 SoC Family"
 	select GPIOLIB
-- 
2.48.1

Re: [PATCH 01/10] arm64: Add SOPHGO SOC family Kconfig support

[Chen Wang]

On 2025/2/10 6:06, Alexander Sverdlin wrote:
> First user will be Aarch64 core within SG2000 SoC.
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>   arch/arm64/Kconfig.platforms | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 02f9248f7c84..f45f3f05edf8 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -307,6 +307,18 @@ config ARCH_INTEL_SOCFPGA
>   	  Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
>   	  Agilex and eASIC N5X.
>   
> +config ARCH_SOPHGO
> +	bool "Sophgo SoCs"
> +	select CLK_SOPHGO_CV1800
> +	select MFD_SYSCON
> +	select RESET_CONTROLLER
> +	help
> +	  This enables support for Sophgo SoC platform hardware, such as
> +	  SG2000.

In the long run, ARCH_SOPHGO will be used to enable all arm64 products 
under Sophgo (although only SG2000 is seen at present), so it is not 
good to limit it to SG2000.

So I suggest you modify the help description here and do not select 
these SG2000-specific configurations. The specific configuration can be 
enabled in defconfig. Please refer to the similar ARCH_SOPHGO processing 
in `arch/riscv/Kconfig.socs`.

Regards,

Chen

> +
> +	  Enable this option if you are going to boot your dual-ARCH SoC in
> +	  ARM64 mode.
> +
>   config ARCH_STM32
>   	bool "STMicroelectronics STM32 SoC Family"
>   	select GPIOLIB

[PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts

[Alexander Sverdlin]

Make the peripheral device tree re-usable on ARM64 platform by splitting it
into CPU-core specific and peripheral parts.

Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
into "plic" interrupt-controller numbering.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++++++++
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +----------------
 3 files changed, 317 insertions(+), 303 deletions(-)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi

diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
index 5fd14dd1b14f..bbdb30653e9a 100644
--- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
@@ -11,7 +11,7 @@ soc {
 		emmc: mmc@4300000 {
 			compatible = "sophgo,cv1800b-dwcmshc";
 			reg = <0x4300000 0x1000>;
-			interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk CLK_AXI4_EMMC>,
 				 <&clk CLK_EMMC>;
 			clock-names = "core", "bus";
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
new file mode 100644
index 000000000000..53834b0658b2
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/clock/sophgo,cv1800.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	osc: oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc_25m";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		clk: clock-controller@3002000 {
+			reg = <0x03002000 0x1000>;
+			clocks = <&osc>;
+			#clock-cells = <1>;
+		};
+
+		gpio0: gpio@3020000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x3020000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio1: gpio@3021000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x3021000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portb: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio2: gpio@3022000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x3022000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portc: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpio3: gpio@3023000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x3023000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			portd: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		saradc: adc@30f0000 {
+			compatible = "sophgo,cv1800b-saradc";
+			reg = <0x030f0000 0x1000>;
+			clocks = <&clk CLK_SARADC>;
+			interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			channel@0 {
+				reg = <0>;
+			};
+
+			channel@1 {
+				reg = <1>;
+			};
+
+			channel@2 {
+				reg = <2>;
+			};
+		};
+
+		i2c0: i2c@4000000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x04000000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
+			clock-names = "ref", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@4010000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x04010000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
+			clock-names = "ref", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@4020000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x04020000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
+			clock-names = "ref", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@4030000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x04030000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
+			clock-names = "ref", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@4040000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x04040000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
+			clock-names = "ref", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart0: serial@4140000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x04140000 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@4150000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x04150000 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@4160000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x04160000 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@4170000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x04170000 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		spi0: spi@4180000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x04180000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
+			clock-names = "ssi_clk", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		spi1: spi@4190000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x04190000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
+			clock-names = "ssi_clk", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		spi2: spi@41a0000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x041a0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
+			clock-names = "ssi_clk", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		spi3: spi@41b0000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x041b0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
+			clock-names = "ssi_clk", "pclk";
+			interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial@41c0000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x041c0000 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		sdhci0: mmc@4310000 {
+			compatible = "sophgo,cv1800b-dwcmshc";
+			reg = <0x4310000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk CLK_AXI4_SD0>,
+				 <&clk CLK_SD0>;
+			clock-names = "core", "bus";
+			status = "disabled";
+		};
+
+		sdhci1: mmc@4320000 {
+			compatible = "sophgo,cv1800b-dwcmshc";
+			reg = <0x4320000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk CLK_AXI4_SD1>,
+				 <&clk CLK_SD1>;
+			clock-names = "core", "bus";
+			status = "disabled";
+		};
+
+		dmac: dma-controller@4330000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0x04330000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
+			clock-names = "core-clk", "cfgr-clk";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+			snps,block-size = <1024 1024 1024 1024
+					   1024 1024 1024 1024>;
+			snps,priority = <0 1 2 3 4 5 6 7>;
+			snps,dma-masters = <2>;
+			snps,data-width = <4>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index c18822ec849f..57a01b71aa67 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -4,9 +4,9 @@
  * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
  */
 
-#include <dt-bindings/clock/sophgo,cv1800.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#define SOC_PERIPHERAL_IRQ(nr)		((nr) + 16)
+
+#include "cv18xx-periph.dtsi"
 
 / {
 	#address-cells = <1>;
@@ -41,310 +41,11 @@ cpu0_intc: interrupt-controller {
 		};
 	};
 
-	osc: oscillator {
-		compatible = "fixed-clock";
-		clock-output-names = "osc_25m";
-		#clock-cells = <0>;
-	};
-
 	soc {
-		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
-		#address-cells = <1>;
-		#size-cells = <1>;
 		dma-noncoherent;
 		ranges;
 
-		clk: clock-controller@3002000 {
-			reg = <0x03002000 0x1000>;
-			clocks = <&osc>;
-			#clock-cells = <1>;
-		};
-
-		gpio0: gpio@3020000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0x3020000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			porta: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		gpio1: gpio@3021000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0x3021000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			portb: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		gpio2: gpio@3022000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0x3022000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			portc: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		gpio3: gpio@3023000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0x3023000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			portd: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		saradc: adc@30f0000 {
-			compatible = "sophgo,cv1800b-saradc";
-			reg = <0x030f0000 0x1000>;
-			clocks = <&clk CLK_SARADC>;
-			interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-
-			channel@0 {
-				reg = <0>;
-			};
-
-			channel@1 {
-				reg = <1>;
-			};
-
-			channel@2 {
-				reg = <2>;
-			};
-		};
-
-		i2c0: i2c@4000000 {
-			compatible = "snps,designware-i2c";
-			reg = <0x04000000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
-			clock-names = "ref", "pclk";
-			interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		i2c1: i2c@4010000 {
-			compatible = "snps,designware-i2c";
-			reg = <0x04010000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
-			clock-names = "ref", "pclk";
-			interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		i2c2: i2c@4020000 {
-			compatible = "snps,designware-i2c";
-			reg = <0x04020000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
-			clock-names = "ref", "pclk";
-			interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		i2c3: i2c@4030000 {
-			compatible = "snps,designware-i2c";
-			reg = <0x04030000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
-			clock-names = "ref", "pclk";
-			interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		i2c4: i2c@4040000 {
-			compatible = "snps,designware-i2c";
-			reg = <0x04040000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
-			clock-names = "ref", "pclk";
-			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		uart0: serial@4140000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x04140000 0x100>;
-			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
-			clock-names = "baudclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart1: serial@4150000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x04150000 0x100>;
-			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
-			clock-names = "baudclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart2: serial@4160000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x04160000 0x100>;
-			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
-			clock-names = "baudclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart3: serial@4170000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x04170000 0x100>;
-			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
-			clock-names = "baudclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		spi0: spi@4180000 {
-			compatible = "snps,dw-apb-ssi";
-			reg = <0x04180000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
-			clock-names = "ssi_clk", "pclk";
-			interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		spi1: spi@4190000 {
-			compatible = "snps,dw-apb-ssi";
-			reg = <0x04190000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
-			clock-names = "ssi_clk", "pclk";
-			interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		spi2: spi@41a0000 {
-			compatible = "snps,dw-apb-ssi";
-			reg = <0x041a0000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
-			clock-names = "ssi_clk", "pclk";
-			interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		spi3: spi@41b0000 {
-			compatible = "snps,dw-apb-ssi";
-			reg = <0x041b0000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
-			clock-names = "ssi_clk", "pclk";
-			interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		uart4: serial@41c0000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x041c0000 0x100>;
-			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
-			clock-names = "baudclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		sdhci0: mmc@4310000 {
-			compatible = "sophgo,cv1800b-dwcmshc";
-			reg = <0x4310000 0x1000>;
-			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_AXI4_SD0>,
-				 <&clk CLK_SD0>;
-			clock-names = "core", "bus";
-			status = "disabled";
-		};
-
-		sdhci1: mmc@4320000 {
-			compatible = "sophgo,cv1800b-dwcmshc";
-			reg = <0x4320000 0x1000>;
-			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_AXI4_SD1>,
-				 <&clk CLK_SD1>;
-			clock-names = "core", "bus";
-			status = "disabled";
-		};
-
-		dmac: dma-controller@4330000 {
-			compatible = "snps,axi-dma-1.01a";
-			reg = <0x04330000 0x1000>;
-			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
-			clock-names = "core-clk", "cfgr-clk";
-			#dma-cells = <1>;
-			dma-channels = <8>;
-			snps,block-size = <1024 1024 1024 1024
-					   1024 1024 1024 1024>;
-			snps,priority = <0 1 2 3 4 5 6 7>;
-			snps,dma-masters = <2>;
-			snps,data-width = <4>;
-			status = "disabled";
-		};
-
 		plic: interrupt-controller@70000000 {
 			reg = <0x70000000 0x4000000>;
 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
-- 
2.48.1

Re: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts

[Inochi Amaoto]

On Sun, Feb 09, 2025 at 11:06:27PM +0100, Alexander Sverdlin wrote:
> Make the peripheral device tree re-usable on ARM64 platform by splitting it
> into CPU-core specific and peripheral parts.
> 
> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> into "plic" interrupt-controller numbering.
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
>  arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +----------------
>  3 files changed, 317 insertions(+), 303 deletions(-)
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> index 5fd14dd1b14f..bbdb30653e9a 100644
> --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> @@ -11,7 +11,7 @@ soc {
>  		emmc: mmc@4300000 {
>  			compatible = "sophgo,cv1800b-dwcmshc";
>  			reg = <0x4300000 0x1000>;
> -			interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&clk CLK_AXI4_EMMC>,
>  				 <&clk CLK_EMMC>;
>  			clock-names = "core", "bus";
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> new file mode 100644
> index 000000000000..53834b0658b2
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> @@ -0,0 +1,313 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> + */
> +

Split the cpu into a separate file and hold the cv18xx.dtsi to
hold the peripheral. Also define the SOC_PERIPHERAL_IRQ in the
cpu file, so you can get less change.

> +#include <dt-bindings/clock/sophgo,cv1800.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	osc: oscillator {
> +		compatible = "fixed-clock";
> +		clock-output-names = "osc_25m";
> +		#clock-cells = <0>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;

You also needs ranges here.

> +
> +		clk: clock-controller@3002000 {
> +			reg = <0x03002000 0x1000>;
> +			clocks = <&osc>;
> +			#clock-cells = <1>;
> +		};
> +

[...]

> +		dmac: dma-controller@4330000 {
> +			compatible = "snps,axi-dma-1.01a";
> +			reg = <0x04330000 0x1000>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
> +			clock-names = "core-clk", "cfgr-clk";
> +			#dma-cells = <1>;
> +			dma-channels = <8>;
> +			snps,block-size = <1024 1024 1024 1024
> +					   1024 1024 1024 1024>;
> +			snps,priority = <0 1 2 3 4 5 6 7>;
> +			snps,dma-masters = <2>;
> +			snps,data-width = <4>;
> +			status = "disabled";
> +		};
> +	};
> +};
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index c18822ec849f..57a01b71aa67 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -4,9 +4,9 @@
>   * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>   */
>  
> -#include <dt-bindings/clock/sophgo,cv1800.h>
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/interrupt-controller/irq.h>
> +#define SOC_PERIPHERAL_IRQ(nr)		((nr) + 16)
> +
> +#include "cv18xx-periph.dtsi"
>  
>  / {
>  	#address-cells = <1>;
> @@ -41,310 +41,11 @@ cpu0_intc: interrupt-controller {
>  		};
>  	};
>  
> -	osc: oscillator {
> -		compatible = "fixed-clock";
> -		clock-output-names = "osc_25m";
> -		#clock-cells = <0>;
> -	};
> -
>  	soc {
> -		compatible = "simple-bus";
>  		interrupt-parent = <&plic>;
> -		#address-cells = <1>;
> -		#size-cells = <1>;

>  		dma-noncoherent;

Move this into new cpu file.

>  		ranges;
>  
> -		clk: clock-controller@3002000 {
> -			reg = <0x03002000 0x1000>;
> -			clocks = <&osc>;
> -			#clock-cells = <1>;
> -		};
> -
> -		gpio0: gpio@3020000 {
> -			compatible = "snps,dw-apb-gpio";
> -			reg = <0x3020000 0x1000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -
> -			porta: gpio-controller@0 {
> -				compatible = "snps,dw-apb-gpio-port";
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				ngpios = <32>;
> -				reg = <0>;
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -				interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> -			};
> -		};
> -
> -		gpio1: gpio@3021000 {
> -			compatible = "snps,dw-apb-gpio";
> -			reg = <0x3021000 0x1000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -
> -			portb: gpio-controller@0 {
> -				compatible = "snps,dw-apb-gpio-port";
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				ngpios = <32>;
> -				reg = <0>;
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> -			};
> -		};
> -
> -		gpio2: gpio@3022000 {
> -			compatible = "snps,dw-apb-gpio";
> -			reg = <0x3022000 0x1000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -
> -			portc: gpio-controller@0 {
> -				compatible = "snps,dw-apb-gpio-port";
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				ngpios = <32>;
> -				reg = <0>;
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -				interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> -			};
> -		};
> -
> -		gpio3: gpio@3023000 {
> -			compatible = "snps,dw-apb-gpio";
> -			reg = <0x3023000 0x1000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -
> -			portd: gpio-controller@0 {
> -				compatible = "snps,dw-apb-gpio-port";
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				ngpios = <32>;
> -				reg = <0>;
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> -			};
> -		};
> -
> -		saradc: adc@30f0000 {
> -			compatible = "sophgo,cv1800b-saradc";
> -			reg = <0x030f0000 0x1000>;
> -			clocks = <&clk CLK_SARADC>;
> -			interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			status = "disabled";
> -
> -			channel@0 {
> -				reg = <0>;
> -			};
> -
> -			channel@1 {
> -				reg = <1>;
> -			};
> -
> -			channel@2 {
> -				reg = <2>;
> -			};
> -		};
> -
> -		i2c0: i2c@4000000 {
> -			compatible = "snps,designware-i2c";
> -			reg = <0x04000000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
> -			clock-names = "ref", "pclk";
> -			interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		i2c1: i2c@4010000 {
> -			compatible = "snps,designware-i2c";
> -			reg = <0x04010000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
> -			clock-names = "ref", "pclk";
> -			interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		i2c2: i2c@4020000 {
> -			compatible = "snps,designware-i2c";
> -			reg = <0x04020000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
> -			clock-names = "ref", "pclk";
> -			interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		i2c3: i2c@4030000 {
> -			compatible = "snps,designware-i2c";
> -			reg = <0x04030000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
> -			clock-names = "ref", "pclk";
> -			interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		i2c4: i2c@4040000 {
> -			compatible = "snps,designware-i2c";
> -			reg = <0x04040000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
> -			clock-names = "ref", "pclk";
> -			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		uart0: serial@4140000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04140000 0x100>;
> -			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
> -			clock-names = "baudclk", "apb_pclk";
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart1: serial@4150000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04150000 0x100>;
> -			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
> -			clock-names = "baudclk", "apb_pclk";
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart2: serial@4160000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04160000 0x100>;
> -			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
> -			clock-names = "baudclk", "apb_pclk";
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		uart3: serial@4170000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x04170000 0x100>;
> -			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
> -			clock-names = "baudclk", "apb_pclk";
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		spi0: spi@4180000 {
> -			compatible = "snps,dw-apb-ssi";
> -			reg = <0x04180000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
> -			clock-names = "ssi_clk", "pclk";
> -			interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		spi1: spi@4190000 {
> -			compatible = "snps,dw-apb-ssi";
> -			reg = <0x04190000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
> -			clock-names = "ssi_clk", "pclk";
> -			interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		spi2: spi@41a0000 {
> -			compatible = "snps,dw-apb-ssi";
> -			reg = <0x041a0000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
> -			clock-names = "ssi_clk", "pclk";
> -			interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		spi3: spi@41b0000 {
> -			compatible = "snps,dw-apb-ssi";
> -			reg = <0x041b0000 0x10000>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
> -			clock-names = "ssi_clk", "pclk";
> -			interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> -			status = "disabled";
> -		};
> -
> -		uart4: serial@41c0000 {
> -			compatible = "snps,dw-apb-uart";
> -			reg = <0x041c0000 0x100>;
> -			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
> -			clock-names = "baudclk", "apb_pclk";
> -			reg-shift = <2>;
> -			reg-io-width = <4>;
> -			status = "disabled";
> -		};
> -
> -		sdhci0: mmc@4310000 {
> -			compatible = "sophgo,cv1800b-dwcmshc";
> -			reg = <0x4310000 0x1000>;
> -			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk CLK_AXI4_SD0>,
> -				 <&clk CLK_SD0>;
> -			clock-names = "core", "bus";
> -			status = "disabled";
> -		};
> -
> -		sdhci1: mmc@4320000 {
> -			compatible = "sophgo,cv1800b-dwcmshc";
> -			reg = <0x4320000 0x1000>;
> -			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk CLK_AXI4_SD1>,
> -				 <&clk CLK_SD1>;
> -			clock-names = "core", "bus";
> -			status = "disabled";
> -		};
> -
> -		dmac: dma-controller@4330000 {
> -			compatible = "snps,axi-dma-1.01a";
> -			reg = <0x04330000 0x1000>;
> -			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
> -			clock-names = "core-clk", "cfgr-clk";
> -			#dma-cells = <1>;
> -			dma-channels = <8>;
> -			snps,block-size = <1024 1024 1024 1024
> -					   1024 1024 1024 1024>;
> -			snps,priority = <0 1 2 3 4 5 6 7>;
> -			snps,dma-masters = <2>;
> -			snps,data-width = <4>;
> -			status = "disabled";
> -		};
> -
>  		plic: interrupt-controller@70000000 {
>  			reg = <0x70000000 0x4000000>;
>  			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> -- 
> 2.48.1
> 

Re: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts

[Krzysztof Kozlowski]

On 09/02/2025 23:06, Alexander Sverdlin wrote:
> Make the peripheral device tree re-usable on ARM64 platform by splitting it
> into CPU-core specific and peripheral parts.
> 
> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> into "plic" interrupt-controller numbering.
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
>  arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +----------------
>  3 files changed, 317 insertions(+), 303 deletions(-)
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> index 5fd14dd1b14f..bbdb30653e9a 100644
> --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> @@ -11,7 +11,7 @@ soc {
>  		emmc: mmc@4300000 {
>  			compatible = "sophgo,cv1800b-dwcmshc";
>  			reg = <0x4300000 0x1000>;
> -			interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&clk CLK_AXI4_EMMC>,
>  				 <&clk CLK_EMMC>;
>  			clock-names = "core", "bus";
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> new file mode 100644
> index 000000000000..53834b0658b2
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> @@ -0,0 +1,313 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> + */
> +
> +#include <dt-bindings/clock/sophgo,cv1800.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	osc: oscillator {
> +		compatible = "fixed-clock";

I really doubt that external oscillator is a peripheral. This is either
part of board or the SoC.


> +		clock-output-names = "osc_25m";
> +		#clock-cells = <0>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;

No, override by phandle/label instead of duplicating SoC.

Best regards,
Krzysztof

Re: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts

[Alexander Sverdlin]

Thanks for quick review Krzysztof!

On Mon, 2025-02-10 at 09:43 +0100, Krzysztof Kozlowski wrote:
> On 09/02/2025 23:06, Alexander Sverdlin wrote:
> > Make the peripheral device tree re-usable on ARM64 platform by splitting it
> > into CPU-core specific and peripheral parts.
> > 
> > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> > into "plic" interrupt-controller numbering.
> > 
> > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> > ---
> >   arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
> >   arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++++++++
> >   arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +----------------
                                 ^^^^^^^^^^^
[1]

> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > @@ -0,0 +1,313 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> > + */
> > +
> > +#include <dt-bindings/clock/sophgo,cv1800.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +	osc: oscillator {
> > +		compatible = "fixed-clock";
> 
> I really doubt that external oscillator is a peripheral. This is either
> part of board or the SoC.

This is actually a problem of the original cv18xx.dtsi [1]. Do you think
I need to fix it as part of my series? This would touch all the pure
RiscV boards (using CV18xx SoCs, not SG200x SoCs), which I could avoid
otherwise.

-- 
Alexander Sverdlin.

Re: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts

[Krzysztof Kozlowski]

On 10/02/2025 14:45, Alexander Sverdlin wrote:
> Thanks for quick review Krzysztof!
> 
> On Mon, 2025-02-10 at 09:43 +0100, Krzysztof Kozlowski wrote:
>> On 09/02/2025 23:06, Alexander Sverdlin wrote:
>>> Make the peripheral device tree re-usable on ARM64 platform by splitting it
>>> into CPU-core specific and peripheral parts.
>>>
>>> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
>>> into "plic" interrupt-controller numbering.
>>>
>>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
>>> ---
>>>   arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
>>>   arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++++++++
>>>   arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +----------------
>                                  ^^^^^^^^^^^
> [1]
> 
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
>>> @@ -0,0 +1,313 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>>> + */
>>> +
>>> +#include <dt-bindings/clock/sophgo,cv1800.h>
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +
>>> +/ {
>>> +	osc: oscillator {
>>> +		compatible = "fixed-clock";
>>
>> I really doubt that external oscillator is a peripheral. This is either
>> part of board or the SoC.
> 
> This is actually a problem of the original cv18xx.dtsi [1]. Do you think
> I need to fix it as part of my series? This would touch all the pure
> RiscV boards (using CV18xx SoCs, not SG200x SoCs), which I could avoid
> otherwise.

You are moving the node out of cv18xx.dtsi, so you can move it to final
place for example. But I do not insist, because I also do not know the
final (truly correct) place - don't know the hardware here.

Best regards,
Krzysztof

Re: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts

[Alexander Sverdlin]

Hi Krzysztof!

On Tue, 2025-02-11 at 09:08 +0100, Krzysztof Kozlowski wrote:
> > > > +/ {
> > > > +	osc: oscillator {
> > > > +		compatible = "fixed-clock";
> > > 
> > > I really doubt that external oscillator is a peripheral. This is either
> > > part of board or the SoC.
> > 
> > This is actually a problem of the original cv18xx.dtsi [1]. Do you think
> > I need to fix it as part of my series? This would touch all the pure
> > RiscV boards (using CV18xx SoCs, not SG200x SoCs), which I could avoid
> > otherwise.
> 
> You are moving the node out of cv18xx.dtsi, so you can move it to final
> place for example. But I do not insist, because I also do not know the
> final (truly correct) place - don't know the hardware here.

Fortunately, problem disappeared by itself in v2 [1], now I don't touch it any longer
and only move CPU and int controller into corresponding SoCs, so the oscillator
falls into "could be coded as a fixed-clock in the SoC DTSI" cathegory of the
coding style.

Link: https://lore.kernel.org/soc/20250210220951.1248533-2-alexander.sverdlin@gmail.com/

-- 
Alexander Sverdlin.

Re: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts

[Alexander Sverdlin]

Hi Krzysztof!

On Mon, 2025-02-10 at 09:43 +0100, Krzysztof Kozlowski wrote:
> > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > new file mode 100644
> > index 000000000000..53834b0658b2
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > @@ -0,0 +1,313 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> > + */
> > +
> > +#include <dt-bindings/clock/sophgo,cv1800.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +	osc: oscillator {
> > +		compatible = "fixed-clock";
> 
> I really doubt that external oscillator is a peripheral. This is either
> part of board or the SoC.
> 
> 
> > +		clock-output-names = "osc_25m";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	soc {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> 
> No, override by phandle/label instead of duplicating SoC.

Is this one critical? Otherwise I struggle in v2 to both keep
SOC_PERIPHERAL_IRQ() in [a new] cv18xx-cpu.dtsi and reference &soc
from cv18xx-cpu.dtsi. It's kind of circular-dependency.

-- 
Alexander Sverdlin.

Re: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts

[Krzysztof Kozlowski]

On 10/02/2025 15:26, Alexander Sverdlin wrote:
> Hi Krzysztof!
> 
> On Mon, 2025-02-10 at 09:43 +0100, Krzysztof Kozlowski wrote:
>>> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
>>> new file mode 100644
>>> index 000000000000..53834b0658b2
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
>>> @@ -0,0 +1,313 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>>> + */
>>> +
>>> +#include <dt-bindings/clock/sophgo,cv1800.h>
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +
>>> +/ {
>>> +	osc: oscillator {
>>> +		compatible = "fixed-clock";
>>
>> I really doubt that external oscillator is a peripheral. This is either
>> part of board or the SoC.
>>
>>
>>> +		clock-output-names = "osc_25m";
>>> +		#clock-cells = <0>;
>>> +	};
>>> +
>>> +	soc {
>>> +		compatible = "simple-bus";
>>> +		#address-cells = <1>;
>>> +		#size-cells = <1>;
>>
>> No, override by phandle/label instead of duplicating SoC.
> 
> Is this one critical? Otherwise I struggle in v2 to both keep

Yes, because duplicated definition is both pain and confusing. It is IMO
semantically not correct - there is only one soc, not two SoCs. If you
have two, then you miss proper unit address.

> SOC_PERIPHERAL_IRQ() in [a new] cv18xx-cpu.dtsi and reference &soc

SOC_PERIPHERAL_IRQ() does not belong here, but to the base DTSI for your
arch. I would rather recommend not to create fake DTSI structure
reflecting some arbitrary choice. cv18xx-cpu.dtsi is not better - for
example type of interrupts are rather arch or GIC specific, not the CPU.
Unless you meant something else by CPU, but then it is getting more
confusing.

Look how others, e.g. Renesas, defines it - no problem overriding soc,
no problem with SOC_PERIPHERAL_IRQ().

> from cv18xx-cpu.dtsi. It's kind of circular-dependency.
> 


Best regards,
Krzysztof

[PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Alexander Sverdlin]

Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi

diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
new file mode 100644
index 000000000000..4e520486cbe5
--- /dev/null
+++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#define SOC_PERIPHERAL_IRQ(nr)		GIC_SPI (nr)
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <riscv/sophgo/cv18xx-periph.dtsi>
+#include <riscv/sophgo/cv181x.dtsi>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "sophgo,sg2000";
+	interrupt-parent = <&gic>;
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x20000000>;	/* 512MiB */
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0>;
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache {
+			compatible = "cache";
+			cache-level= <2>;
+			cache-size = <0x20000>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+		always-on;
+		clock-frequency = <25000000>;
+	};
+
+	gic: interrupt-controller@1f01000 {
+		compatible = "arm,cortex-a15-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x01f01000 0x1000>,
+		      <0x01f02000 0x2000>;
+	};
+
+	soc {
+		ranges;
+
+		pinctrl: pinctrl@3001000 {
+			compatible = "sophgo,sg2000-pinctrl";
+			reg = <0x03001000 0x1000>,
+			      <0x05027000 0x1000>;
+			reg-names = "sys", "rtc";
+		};
+	};
+};
+
+
+&clk {
+	compatible = "sophgo,sg2000-clk";
+};
-- 
2.48.1

Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Inochi Amaoto]

On Sun, Feb 09, 2025 at 11:06:28PM +0100, Alexander Sverdlin wrote:
> Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>

Can you add a riscv version of the this file too? This also applies
to patch 4 and 5

Regards,
Inochi

> ---
>  arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++
>  1 file changed, 79 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
> 
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> new file mode 100644
> index 000000000000..4e520486cbe5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#define SOC_PERIPHERAL_IRQ(nr)		GIC_SPI (nr)
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <riscv/sophgo/cv18xx-periph.dtsi>
> +#include <riscv/sophgo/cv181x.dtsi>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	compatible = "sophgo,sg2000";
> +	interrupt-parent = <&gic>;
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x20000000>;	/* 512MiB */
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0>;
> +			i-cache-size = <32768>;
> +			d-cache-size = <32768>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		l2: l2-cache {
> +			compatible = "cache";
> +			cache-level= <2>;
> +			cache-size = <0x20000>;
> +		};
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +		always-on;
> +		clock-frequency = <25000000>;
> +	};
> +
> +	gic: interrupt-controller@1f01000 {
> +		compatible = "arm,cortex-a15-gic";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		reg = <0x01f01000 0x1000>,
> +		      <0x01f02000 0x2000>;
> +	};
> +
> +	soc {
> +		ranges;
> +
> +		pinctrl: pinctrl@3001000 {
> +			compatible = "sophgo,sg2000-pinctrl";
> +			reg = <0x03001000 0x1000>,
> +			      <0x05027000 0x1000>;
> +			reg-names = "sys", "rtc";
> +		};
> +	};
> +};
> +
> +
> +&clk {
> +	compatible = "sophgo,sg2000-clk";
> +};
> -- 
> 2.48.1
> 

Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Alexander Sverdlin]

Hi Inochi,

On Mon, 2025-02-10 at 13:05 +0800, Inochi Amaoto wrote:
> > Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
> > 
> > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> 
> Can you add a riscv version of the this file too? This also applies
> to patch 4 and 5

this would require binary Sophgo RiscV toolchain, which was the whole
point of my ARM64 BSP. So, while I could add RiscV counterparts, they
would be completely untested.

On the macro level that how I see the current state of upstream affairs:

RiscV:
There are necessary upstream packages available required to boot, but
there is no upstream toolchain to build them.

ARM64:
There is an upstream toolchain, but the published U-Boot is being
linked with ATF binaries -- I was planning to come up with pure
U-Boot BSP for this, without binary blobs.

-- 
Alexander Sverdlin.

Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Inochi Amaoto]

On Sun, Feb 09, 2025 at 11:06:28PM +0100, Alexander Sverdlin wrote:
> Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++
>  1 file changed, 79 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
> 
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> new file mode 100644
> index 000000000000..4e520486cbe5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#define SOC_PERIPHERAL_IRQ(nr)		GIC_SPI (nr)
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <riscv/sophgo/cv18xx-periph.dtsi>
> +#include <riscv/sophgo/cv181x.dtsi>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	compatible = "sophgo,sg2000";
> +	interrupt-parent = <&gic>;
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x20000000>;	/* 512MiB */
> +	};
> +

> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0>;
> +			i-cache-size = <32768>;
> +			d-cache-size = <32768>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		l2: l2-cache {
> +			compatible = "cache";
> +			cache-level= <2>;
> +			cache-size = <0x20000>;
> +		};
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +		always-on;
> +		clock-frequency = <25000000>;
> +	};
> +
> +	gic: interrupt-controller@1f01000 {
> +		compatible = "arm,cortex-a15-gic";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		reg = <0x01f01000 0x1000>,
> +		      <0x01f02000 0x2000>;
> +	};
> +

Separate these into a separate CPU file so SG2002 can reuse it.

> +	soc {
> +		ranges;
> +
> +		pinctrl: pinctrl@3001000 {
> +			compatible = "sophgo,sg2000-pinctrl";
> +			reg = <0x03001000 0x1000>,
> +			      <0x05027000 0x1000>;
> +			reg-names = "sys", "rtc";
> +		};
> +	};
> +};
> +
> +
> +&clk {
> +	compatible = "sophgo,sg2000-clk";
> +};
> -- 
> 2.48.1
> 

Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Krzysztof Kozlowski]

On 09/02/2025 23:06, Alexander Sverdlin wrote:
> Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++
>  1 file changed, 79 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
> 
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> new file mode 100644
> index 000000000000..4e520486cbe5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#define SOC_PERIPHERAL_IRQ(nr)		GIC_SPI (nr)
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <riscv/sophgo/cv18xx-periph.dtsi>
> +#include <riscv/sophgo/cv181x.dtsi>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	compatible = "sophgo,sg2000";
> +	interrupt-parent = <&gic>;
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x20000000>;	/* 512MiB */
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0>;
> +			i-cache-size = <32768>;
> +			d-cache-size = <32768>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		l2: l2-cache {
> +			compatible = "cache";
> +			cache-level= <2>;
> +			cache-size = <0x20000>;
> +		};
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +		always-on;
> +		clock-frequency = <25000000>;
> +	};
> +
> +	gic: interrupt-controller@1f01000 {

MMIO nodes are always in the soc.

> +		compatible = "arm,cortex-a15-gic";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		reg = <0x01f01000 0x1000>,
> +		      <0x01f02000 0x2000>;
> +	};
> +
> +	soc {

Override by phandle/label instead of duplicating.

> +		ranges;
> +
> +		pinctrl: pinctrl@3001000 {
> +			compatible = "sophgo,sg2000-pinctrl";
> +			reg = <0x03001000 0x1000>,
> +			      <0x05027000 0x1000>;
> +			reg-names = "sys", "rtc";
> +		};
> +	};
> +};
> +
> +
> +&clk {
> +	compatible = "sophgo,sg2000-clk";


That's discouraged practice. If you need to define compatible, it means
the block is not shared between designs and must not be in common DTSI.


Best regards,
Krzysztof

Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Alexander Sverdlin]

Hi Krzysztof!

On Mon, 2025-02-10 at 09:45 +0100, Krzysztof Kozlowski wrote:
> On 09/02/2025 23:06, Alexander Sverdlin wrote:
> > Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
> > 
> > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> > ---
> >   arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++
> >   1 file changed, 79 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> > new file mode 100644
> > index 000000000000..4e520486cbe5
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> > @@ -0,0 +1,79 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +
> > +#define SOC_PERIPHERAL_IRQ(nr)		GIC_SPI (nr)
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <riscv/sophgo/cv18xx-periph.dtsi>
> > +#include <riscv/sophgo/cv181x.dtsi>
> > +
> > +/ {

[...]

> > +	gic: interrupt-controller@1f01000 {
> 
> MMIO nodes are always in the soc.

I think I've looked a wrong example (or a counter-example)...
$ grep -R -P '^\t\tcompatible = "arm,cortex-a15-gic";' *
arm/boot/dts/intel/axm/axm55xx.dtsi:		compatible = "arm,cortex-a15-gic";
arm/boot/dts/ti/omap/dra7.dtsi:		compatible = "arm,cortex-a15-gic";
arm/boot/dts/ti/omap/omap5.dtsi:		compatible = "arm,cortex-a15-gic";
arm/boot/dts/nvidia/tegra124.dtsi:		compatible = "arm,cortex-a15-gic";
arm/boot/dts/nvidia/tegra114.dtsi:		compatible = "arm,cortex-a15-gic";
arm64/boot/dts/nvidia/tegra132.dtsi:		compatible = "arm,cortex-a15-gic";
arm64/boot/dts/freescale/s32v234.dtsi:		compatible = "arm,cortex-a15-gic";
arm64/boot/dts/apm/apm-storm.dtsi:		compatible = "arm,cortex-a15-gic";
arm64/boot/dts/apm/apm-shadowcat.dtsi:		compatible = "arm,cortex-a15-gic";

But thanks for clarification!

> > +		compatible = "arm,cortex-a15-gic";
> > +		interrupt-controller;
> > +		#interrupt-cells = <3>;
> > +		reg = <0x01f01000 0x1000>,
> > +		      <0x01f02000 0x2000>;
> > +	};
> > +
> > +	soc {
> 
> Override by phandle/label instead of duplicating.
> 
> > +		ranges;
> > +
> > +		pinctrl: pinctrl@3001000 {
> > +			compatible = "sophgo,sg2000-pinctrl";
> > +			reg = <0x03001000 0x1000>,
> > +			      <0x05027000 0x1000>;
> > +			reg-names = "sys", "rtc";
> > +		};
> > +	};
> > +};
> > +
> > +
> > +&clk {
> > +	compatible = "sophgo,sg2000-clk";
> 
> 
> That's discouraged practice. If you need to define compatible, it means
> the block is not shared between designs and must not be in common DTSI.

That doesn't come from my series, that's how original cv18xx.dtsi has been
designed. Same question as before: do I need to rework it if I will not be able to
test the changes (I don't even posess the relevant HW). But if not, I have
to adapt the same pattern into the new sg2000.dtsi.

-- 
Alexander Sverdlin.

Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Krzysztof Kozlowski]

On 10/02/2025 16:01, Alexander Sverdlin wrote:
> Hi Krzysztof!
> 
> On Mon, 2025-02-10 at 09:45 +0100, Krzysztof Kozlowski wrote:
>> On 09/02/2025 23:06, Alexander Sverdlin wrote:
>>> Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
>>>
>>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
>>> ---
>>>   arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++
>>>   1 file changed, 79 insertions(+)
>>>   create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
>>> new file mode 100644
>>> index 000000000000..4e520486cbe5
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
>>> @@ -0,0 +1,79 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +
>>> +#define SOC_PERIPHERAL_IRQ(nr)		GIC_SPI (nr)
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <riscv/sophgo/cv18xx-periph.dtsi>
>>> +#include <riscv/sophgo/cv181x.dtsi>
>>> +
>>> +/ {
> 
> [...]
> 
>>> +	gic: interrupt-controller@1f01000 {
>>
>> MMIO nodes are always in the soc.
> 
> I think I've looked a wrong example (or a counter-example)...
> $ grep -R -P '^\t\tcompatible = "arm,cortex-a15-gic";' *
> arm/boot/dts/intel/axm/axm55xx.dtsi:		compatible = "arm,cortex-a15-gic";
> arm/boot/dts/ti/omap/dra7.dtsi:		compatible = "arm,cortex-a15-gic";
> arm/boot/dts/ti/omap/omap5.dtsi:		compatible = "arm,cortex-a15-gic";
> arm/boot/dts/nvidia/tegra124.dtsi:		compatible = "arm,cortex-a15-gic";
> arm/boot/dts/nvidia/tegra114.dtsi:		compatible = "arm,cortex-a15-gic";

These are all old.

> arm64/boot/dts/nvidia/tegra132.dtsi:		compatible = "arm,cortex-a15-gic";
> arm64/boot/dts/freescale/s32v234.dtsi:		compatible = "arm,cortex-a15-gic";

Well, it happens.

> arm64/boot/dts/apm/apm-storm.dtsi:		compatible = "arm,cortex-a15-gic";
> arm64/boot/dts/apm/apm-shadowcat.dtsi:		compatible = "arm,cortex-a15-gic";

These are strong anti-patterns. Unmaintained.

> 
> But thanks for clarification!
> 
>>> +		compatible = "arm,cortex-a15-gic";
>>> +		interrupt-controller;
>>> +		#interrupt-cells = <3>;
>>> +		reg = <0x01f01000 0x1000>,
>>> +		      <0x01f02000 0x2000>;
>>> +	};
>>> +
>>> +	soc {
>>
>> Override by phandle/label instead of duplicating.
>>
>>> +		ranges;
>>> +
>>> +		pinctrl: pinctrl@3001000 {
>>> +			compatible = "sophgo,sg2000-pinctrl";
>>> +			reg = <0x03001000 0x1000>,
>>> +			      <0x05027000 0x1000>;
>>> +			reg-names = "sys", "rtc";
>>> +		};
>>> +	};
>>> +};
>>> +
>>> +
>>> +&clk {
>>> +	compatible = "sophgo,sg2000-clk";
>>
>>
>> That's discouraged practice. If you need to define compatible, it means
>> the block is not shared between designs and must not be in common DTSI.
> 
> That doesn't come from my series, that's how original cv18xx.dtsi has been

You can change the other file to match real hardware. But if original
cv18xx.dtsi has incorrect or imprecise compatible, I wonder how does it
work....

> designed. Same question as before: do I need to rework it if I will not be able to
> test the changes (I don't even posess the relevant HW). But if not, I have
> to adapt the same pattern into the new sg2000.dtsi.





Best regards,
Krzysztof

Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Alexander Sverdlin]

Hi Krzysztof!

On Tue, 2025-02-11 at 09:07 +0100, Krzysztof Kozlowski wrote:
> > > > +&clk {
> > > > +	compatible = "sophgo,sg2000-clk";
> > > 
> > > 
> > > That's discouraged practice. If you need to define compatible, it means
> > > the block is not shared between designs and must not be in common DTSI.
> > 
> > That doesn't come from my series, that's how original cv18xx.dtsi has been
> 
> You can change the other file to match real hardware. But if original
> cv18xx.dtsi has incorrect or imprecise compatible, I wonder how does it
> work....

cv18xx.dtsi doesn't have any "compatible". They define it for every SoC individually.
So it's same MMIO window, different compatible. Looking into the driver I can tell
that even the register map is the same, but they expose (and pre-enable) different
subsets on different SoCs.

-- 
Alexander Sverdlin.

Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree

[Krzysztof Kozlowski]

On 11/02/2025 10:22, Alexander Sverdlin wrote:
> Hi Krzysztof!
> 
> On Tue, 2025-02-11 at 09:07 +0100, Krzysztof Kozlowski wrote:
>>>>> +&clk {
>>>>> +	compatible = "sophgo,sg2000-clk";
>>>>
>>>>
>>>> That's discouraged practice. If you need to define compatible, it means
>>>> the block is not shared between designs and must not be in common DTSI.
>>>
>>> That doesn't come from my series, that's how original cv18xx.dtsi has been
>>
>> You can change the other file to match real hardware. But if original
>> cv18xx.dtsi has incorrect or imprecise compatible, I wonder how does it
>> work....
> 
> cv18xx.dtsi doesn't have any "compatible". They define it for every SoC individually.
> So it's same MMIO window, different compatible. Looking into the driver I can tell
> that even the register map is the same, but they expose (and pre-enable) different
> subsets on different SoCs.

OK, so this follows established practice for this soc. Fine with me.

Best regards,
Krzysztof

[PATCH 04/10] arm64: dts: sophgo: Add Duo Module 01

[Alexander Sverdlin]

The Duo Module 01 is a compact module with integrated SG2000,
WI-FI6/BTDM5.4, and eMMC.
Add only support for UART and SDHCI.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 .../sophgo/sg2000_milkv_duo_module_01.dtsi    | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi

diff --git a/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
new file mode 100644
index 000000000000..7edcc4d03cc4
--- /dev/null
+++ b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
+#include "sg2000.dtsi"
+
+/ {
+	model = "Milk-V Duo Module 01";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+};
+
+&osc {
+	clock-frequency = <25000000>;
+};
+
+&emmc {
+	/delete-property/ status;
+	bus-width = <4>;
+	no-1-8-v;
+	cap-mmc-hw-reset;
+	no-sd;
+	no-sdio;
+	non-removable;
+};
+
+/* Wi-Fi */
+&sdhci1 {
+	bus-width = <4>;
+	cap-sdio-irq;
+	no-mmc;
+	no-sd;
+	non-removable;
+};
+
+&pinctrl {
+	uart0_cfg: uart0-cfg {
+		uart0-pins {
+			pinmux = <PINMUX(PIN_UART0_TX, 0)>,
+				 <PINMUX(PIN_UART0_RX, 0)>;
+			bias-pull-up;
+			drive-strength-microamp = <10800>;
+			power-source = <3300>;
+		};
+	};
+
+	sdhci0_cfg: sdhci0-cfg {
+		sdhci0-clk-pins {
+			pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
+			bias-pull-up;
+			drive-strength-microamp = <16100>;
+			power-source = <3300>;
+		};
+
+		sdhci0-cmd-pins {
+			pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
+			bias-pull-up;
+			drive-strength-microamp = <10800>;
+			power-source = <3300>;
+		};
+
+		sdhci0-data-pins {
+			pinmux = <PINMUX(PIN_SD0_D0, 0)>,
+				 <PINMUX(PIN_SD0_D1, 0)>,
+				 <PINMUX(PIN_SD0_D2, 0)>,
+				 <PINMUX(PIN_SD0_D3, 0)>;
+			bias-pull-up;
+			drive-strength-microamp = <10800>;
+			power-source = <3300>;
+		};
+
+		sdhci0-cd-pins {
+			pinmux = <PINMUX(PIN_SD0_CD, 0)>;
+			bias-pull-up;
+			drive-strength-microamp = <10800>;
+			power-source = <3300>;
+		};
+	};
+};
-- 
2.48.1

Re: [PATCH 04/10] arm64: dts: sophgo: Add Duo Module 01

[Inochi Amaoto]

On Sun, Feb 09, 2025 at 11:06:29PM +0100, Alexander Sverdlin wrote:
> The Duo Module 01 is a compact module with integrated SG2000,
> WI-FI6/BTDM5.4, and eMMC.
> Add only support for UART and SDHCI.
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  .../sophgo/sg2000_milkv_duo_module_01.dtsi    | 84 +++++++++++++++++++
>  1 file changed, 84 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
> 
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
> new file mode 100644
> index 000000000000..7edcc4d03cc4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
> +#include "sg2000.dtsi"
> +
> +/ {
> +	model = "Milk-V Duo Module 01";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +	};
> +};
> +
> +&osc {
> +	clock-frequency = <25000000>;
> +};
> +
> +&emmc {

> +	/delete-property/ status;

Override it with status = "okay";
This suggestion applies to all you dts patch.

> +	bus-width = <4>;
> +	no-1-8-v;
> +	cap-mmc-hw-reset;
> +	no-sd;
> +	no-sdio;
> +	non-removable;
> +};
> +
> +/* Wi-Fi */
> +&sdhci1 {
> +	bus-width = <4>;
> +	cap-sdio-irq;
> +	no-mmc;
> +	no-sd;
> +	non-removable;
> +};
> +
> +&pinctrl {
> +	uart0_cfg: uart0-cfg {
> +		uart0-pins {
> +			pinmux = <PINMUX(PIN_UART0_TX, 0)>,
> +				 <PINMUX(PIN_UART0_RX, 0)>;
> +			bias-pull-up;
> +			drive-strength-microamp = <10800>;
> +			power-source = <3300>;
> +		};
> +	};
> +
> +	sdhci0_cfg: sdhci0-cfg {
> +		sdhci0-clk-pins {
> +			pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
> +			bias-pull-up;
> +			drive-strength-microamp = <16100>;
> +			power-source = <3300>;
> +		};
> +
> +		sdhci0-cmd-pins {
> +			pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
> +			bias-pull-up;
> +			drive-strength-microamp = <10800>;
> +			power-source = <3300>;
> +		};
> +
> +		sdhci0-data-pins {
> +			pinmux = <PINMUX(PIN_SD0_D0, 0)>,
> +				 <PINMUX(PIN_SD0_D1, 0)>,
> +				 <PINMUX(PIN_SD0_D2, 0)>,
> +				 <PINMUX(PIN_SD0_D3, 0)>;
> +			bias-pull-up;
> +			drive-strength-microamp = <10800>;
> +			power-source = <3300>;
> +		};
> +
> +		sdhci0-cd-pins {
> +			pinmux = <PINMUX(PIN_SD0_CD, 0)>;
> +			bias-pull-up;
> +			drive-strength-microamp = <10800>;
> +			power-source = <3300>;
> +		};
> +	};
> +};
> -- 
> 2.48.1
> 

Re: [PATCH 04/10] arm64: dts: sophgo: Add Duo Module 01

[Krzysztof Kozlowski]

On 09/02/2025 23:06, Alexander Sverdlin wrote:
> The Duo Module 01 is a compact module with integrated SG2000,
> WI-FI6/BTDM5.4, and eMMC.
> Add only support for UART and SDHCI.
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  .../sophgo/sg2000_milkv_duo_module_01.dtsi    | 84 +++++++++++++++++++
>  1 file changed, 84 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
> 
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
> new file mode 100644
> index 000000000000..7edcc4d03cc4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi

Underscores are almost never used in DTS file names. Don't grow this
pattern.

> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
> +#include "sg2000.dtsi"
> +
> +/ {
> +	model = "Milk-V Duo Module 01";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +	};
> +};
> +
> +&osc {
> +	clock-frequency = <25000000>;
> +};
> +
> +&emmc {

Keep ordering according to DTS coding style.


Best regards,
Krzysztof

[PATCH 05/10] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board

[Alexander Sverdlin]

Duo Module 01 Evaluation Board contains Sophgo Duo Module 01
SMD SoM, Ethernet+USB switch, microSD slot, etc...
Add only support for UART0 (console) and microSD slot.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 arch/arm64/boot/dts/Makefile                  |  1 +
 arch/arm64/boot/dts/sophgo/Makefile           |  2 ++
 .../sophgo/sg2000_milkv_duo_module_01_evb.dts | 30 +++++++++++++++++++
 3 files changed, 33 insertions(+)
 create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
 create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc2..3a32b157ac8c 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -28,6 +28,7 @@ subdir-y += realtek
 subdir-y += renesas
 subdir-y += rockchip
 subdir-y += socionext
+subdir-y += sophgo
 subdir-y += sprd
 subdir-y += st
 subdir-y += synaptics
diff --git a/arch/arm64/boot/dts/sophgo/Makefile b/arch/arm64/boot/dts/sophgo/Makefile
new file mode 100644
index 000000000000..fcabaf0babf4
--- /dev/null
+++ b/arch/arm64/boot/dts/sophgo/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2000_milkv_duo_module_01_evb.dtb
diff --git a/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts
new file mode 100644
index 000000000000..f3533892453d
--- /dev/null
+++ b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "sg2000_milkv_duo_module_01.dtsi"
+
+/ {
+	model = "Milk-V Duo Module 01 Evaluation Board";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&sdhci0 {
+	/delete-property/ status;
+	bus-width = <4>;
+	no-1-8-v;
+	no-mmc;
+	no-sdio;
+	disable-wp;
+	pinctrl-0 = <&sdhci0_cfg>;
+	pinctrl-names = "default";
+};
+
+&uart0 {
+	/delete-property/ status;
+	pinctrl-0 = <&uart0_cfg>;
+	pinctrl-names = "default";
+};
-- 
2.48.1

Re: [PATCH 05/10] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board

[Krzysztof Kozlowski]

On 09/02/2025 23:06, Alexander Sverdlin wrote:
> diff --git a/arch/arm64/boot/dts/sophgo/Makefile b/arch/arm64/boot/dts/sophgo/Makefile
> new file mode 100644
> index 000000000000..fcabaf0babf4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2000_milkv_duo_module_01_evb.dtb
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts
> new file mode 100644
> index 000000000000..f3533892453d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +/dts-v1/;
> +
> +#include "sg2000_milkv_duo_module_01.dtsi"
> +
> +/ {
> +	model = "Milk-V Duo Module 01 Evaluation Board";

Missing compatible.


Best regards,
Krzysztof

[PATCH 06/10] dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl compatible

[Alexander Sverdlin]

These syscon blocks will be used for CV18xx reset driver.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 4d67ff26d445..5a0b102d1bd9 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -108,6 +108,8 @@ select:
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
           - rockchip,rv1126-qos
+          - sophgo,cv1800-rtcsys-core
+          - sophgo,cv1800-rtcsys-ctrl
           - st,spear1340-misc
           - stericsson,nomadik-pmu
           - starfive,jh7100-sysmain
@@ -207,6 +209,8 @@ properties:
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
           - rockchip,rv1126-qos
+          - sophgo,cv1800-rtcsys-core
+          - sophgo,cv1800-rtcsys-ctrl
           - st,spear1340-misc
           - stericsson,nomadik-pmu
           - starfive,jh7100-sysmain
-- 
2.48.1

Re: [PATCH 06/10] dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl compatible

[Inochi Amaoto]

On Sun, Feb 09, 2025 at 11:06:31PM +0100, Alexander Sverdlin wrote:
> These syscon blocks will be used for CV18xx reset driver.
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  Documentation/devicetree/bindings/mfd/syscon.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index 4d67ff26d445..5a0b102d1bd9 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -108,6 +108,8 @@ select:
>            - rockchip,rk3576-qos
>            - rockchip,rk3588-qos
>            - rockchip,rv1126-qos
> +          - sophgo,cv1800-rtcsys-core
> +          - sophgo,cv1800-rtcsys-ctrl
>            - st,spear1340-misc
>            - stericsson,nomadik-pmu
>            - starfive,jh7100-sysmain
> @@ -207,6 +209,8 @@ properties:
>            - rockchip,rk3576-qos
>            - rockchip,rk3588-qos
>            - rockchip,rv1126-qos
> +          - sophgo,cv1800-rtcsys-core
> +          - sophgo,cv1800-rtcsys-ctrl
>            - st,spear1340-misc
>            - stericsson,nomadik-pmu
>            - starfive,jh7100-sysmain
> -- 
> 2.48.1
> 

No cv1800, use cv1800b as the base one.

Regards,
Inochi

Re: [PATCH 06/10] dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl compatible

[Krzysztof Kozlowski]

On 09/02/2025 23:06, Alexander Sverdlin wrote:
> These syscon blocks will be used for CV18xx reset driver.


No, implement proper reset block instead of abusing syscon.

Best regards,
Krzysztof

Re: [PATCH 06/10] dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl compatible

[Alexander Sverdlin]

Hi Krzysztof!

On Mon, 2025-02-10 at 09:48 +0100, Krzysztof Kozlowski wrote:
> On 09/02/2025 23:06, Alexander Sverdlin wrote:
> > These syscon blocks will be used for CV18xx reset driver.
> 
> 
> No, implement proper reset block instead of abusing syscon.

I don't think it's an abuse... You need to look into the corresponding TRM [1].

4 bits I need to tweak (and one magic number into unlock register) are randomly
placed at random memory adresses and otherwise adjacent bits have random
unrelated functions from random unrelated subsystems.
If it's not syscon, I don't know what it is.

It has a reset HW block, as you and Inochi have correctly pointed out, for other
purposes, for resetting the SoC IP blocks. The overall SoC reset is complete
mamba jamba.

I was thinking now about a syscon driver, which will register_restart_handler()...

Inochi, do you have more insights into it? You've mentioned RTC and 8051...
Looking into TRM I don't get it, why a thing blessed to do all the housekeeping
(and called "System Controller" in imx8, for instance) happen to have RTC_ prefix...
Would RTC subsystem maintainer be happy with a monster driver which has ties
to all other subsystems?

[1] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
("rtc_ctrl_unlockkey", "rtc_ctrl0", "RTC_EN_WARM_RST_REQ", "RTC_EN_PWR_CYC_REQ").

-- 
Alexander Sverdlin.

Re: [PATCH 06/10] dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl compatible

[Alexander Sverdlin]

On Mon, 2025-02-10 at 21:30 +0100, Alexander Sverdlin wrote:
> On Mon, 2025-02-10 at 09:48 +0100, Krzysztof Kozlowski wrote:
> > On 09/02/2025 23:06, Alexander Sverdlin wrote:
> > > These syscon blocks will be used for CV18xx reset driver.
> > 
> > 
> > No, implement proper reset block instead of abusing syscon.
> 
> I don't think it's an abuse... You need to look into the corresponding TRM [1].
> 
> 4 bits I need to tweak (and one magic number into unlock register) are randomly
> placed at random memory adresses and otherwise adjacent bits have random
> unrelated functions from random unrelated subsystems.
> If it's not syscon, I don't know what it is.
> 
> It has a reset HW block, as you and Inochi have correctly pointed out, for other
> purposes, for resetting the SoC IP blocks. The overall SoC reset is complete
> mamba jamba.
> 
> I was thinking now about a syscon driver, which will register_restart_handler()...

Sorry, I meant "MFD" driver...

> Inochi, do you have more insights into it? You've mentioned RTC and 8051...
> Looking into TRM I don't get it, why a thing blessed to do all the housekeeping
> (and called "System Controller" in imx8, for instance) happen to have RTC_ prefix...
> Would RTC subsystem maintainer be happy with a monster driver which has ties
> to all other subsystems?
> 
> [1] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> ("rtc_ctrl_unlockkey", "rtc_ctrl0", "RTC_EN_WARM_RST_REQ", "RTC_EN_PWR_CYC_REQ").

-- 
Alexander Sverdlin.

[PATCH 07/10] dt-bindings: reset: sophgo: Add CV18xx reset controller

[Alexander Sverdlin]

Add DT bindings for CV18xx reset controller. The power/reboot driver is
going to use only 4 bits from two different MMIO regions which can be
potentially used by other subsystems/drivers, therefore the resources
are not being claimed directly by the device/driver, but via syscons
instead.

Link: https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 .../bindings/reset/sophgo,cv1800-reset.yaml   | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
new file mode 100644
index 000000000000..4f058f99df5f
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/sophgo,cv1800-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cvitek CV18xx/Sophgo SG2000 Reset Controller
+
+maintainers:
+  - Alexander Sverdlin <alexander.sverdlin@gmail.com>
+
+properties:
+  compatible:
+    const: sophgo,cv1800-reset
+
+  sophgo,rtcsys-ctrl:
+    description: phandle of the "RTCSYS_CTRL" syscon block
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  sophgo,rtcsys-core:
+    description: phandle of the "RTCSYS_CORE" syscon block
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+  - compatible
+  - sophgo,rtcsys-ctrl
+  - sophgo,rtcsys-core
+
+additionalProperties: false
+
+examples:
+  - |
+    soc-reset {
+        compatible = "sophgo,cv1800-reset";
+        sophgo,rtcsys-ctrl = <&rtcsys_ctrl>;
+        sophgo,rtcsys-core = <&rtcsys_core>;
+    };
+...
-- 
2.48.1

Re: [PATCH 07/10] dt-bindings: reset: sophgo: Add CV18xx reset controller

[Inochi Amaoto]

On Sun, Feb 09, 2025 at 11:06:32PM +0100, Alexander Sverdlin wrote:
> Add DT bindings for CV18xx reset controller. The power/reboot driver is
> going to use only 4 bits from two different MMIO regions which can be
> potentially used by other subsystems/drivers, therefore the resources
> are not being claimed directly by the device/driver, but via syscons
> instead.
> 
> Link: https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  .../bindings/reset/sophgo,cv1800-reset.yaml   | 38 +++++++++++++++++++
>  1 file changed, 38 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
> new file mode 100644
> index 000000000000..4f058f99df5f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
> @@ -0,0 +1,38 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/sophgo,cv1800-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cvitek CV18xx/Sophgo SG2000 Reset Controller
> +
> +maintainers:
> +  - Alexander Sverdlin <alexander.sverdlin@gmail.com>
> +
> +properties:
> +  compatible:
> +    const: sophgo,cv1800-reset

Please use cv1800b, not cv1800. And this is a reboot device
not reset device. Refer other bindings to write yours.

Regards,
Inochi

Re: [PATCH 07/10] dt-bindings: reset: sophgo: Add CV18xx reset controller

[Krzysztof Kozlowski]

On 09/02/2025 23:06, Alexander Sverdlin wrote:
> Add DT bindings for CV18xx reset controller. The power/reboot driver is
> going to use only 4 bits from two different MMIO regions which can be
> potentially used by other subsystems/drivers, therefore the resources
> are not being claimed directly by the device/driver, but via syscons
> instead.
> 
> Link: https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  .../bindings/reset/sophgo,cv1800-reset.yaml   | 38 +++++++++++++++++++
>  1 file changed, 38 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
> new file mode 100644
> index 000000000000..4f058f99df5f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
> @@ -0,0 +1,38 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/sophgo,cv1800-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cvitek CV18xx/Sophgo SG2000 Reset Controller
> +
> +maintainers:
> +  - Alexander Sverdlin <alexander.sverdlin@gmail.com>
> +
> +properties:
> +  compatible:
> +    const: sophgo,cv1800-reset
> +

Missing reset cells.

> +  sophgo,rtcsys-ctrl:
> +    description: phandle of the "RTCSYS_CTRL" syscon block
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +
> +  sophgo,rtcsys-core:
> +    description: phandle of the "RTCSYS_CORE" syscon block
> +    $ref: /schemas/types.yaml#/definitions/phandle

This does not look right - entirely fake device. And your DTS next patch
proves it.

> +
> +required:
> +  - compatible
> +  - sophgo,rtcsys-ctrl
> +  - sophgo,rtcsys-core
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    soc-reset {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


> +        compatible = "sophgo,cv1800-reset";
> +        sophgo,rtcsys-ctrl = <&rtcsys_ctrl>;
> +        sophgo,rtcsys-core = <&rtcsys_core>;
> +    };
> +...


Best regards,
Krzysztof

[PATCH 08/10] riscv/arm64: dts: cv18xx: Add sysctl and reset nodes

[Alexander Sverdlin]

Add reset controller node and required sysctl nodes.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
index 53834b0658b2..d793b6db4ed1 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
@@ -309,5 +309,21 @@ dmac: dma-controller@4330000 {
 			snps,data-width = <4>;
 			status = "disabled";
 		};
+
+		rtcsys_ctrl: syscon@5025000 {
+			compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon";
+			reg = <0x05025000 0x1000>;
+		};
+
+		rtcsys_core: syscon@5026000 {
+			compatible = "sophgo,cv1800-rtcsys-core", "syscon";
+			reg = <0x05026000 0x1000>;
+		};
+
+		soc-reset {
+			compatible = "sophgo,cv1800-reset";
+			sophgo,rtcsys-ctrl = <&rtcsys_ctrl>;
+			sophgo,rtcsys-core = <&rtcsys_core>;
+		};
 	};
 };
-- 
2.48.1

Re: [PATCH 08/10] riscv/arm64: dts: cv18xx: Add sysctl and reset nodes

[Inochi Amaoto]

On Sun, Feb 09, 2025 at 11:06:33PM +0100, Alexander Sverdlin wrote:
> Add reset controller node and required sysctl nodes.
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> index 53834b0658b2..d793b6db4ed1 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 {
>  			snps,data-width = <4>;
>  			status = "disabled";
>  		};
> +

> +		rtcsys_ctrl: syscon@5025000 {
> +			compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon";
> +			reg = <0x05025000 0x1000>;
> +		};
> +
> +		rtcsys_core: syscon@5026000 {
> +			compatible = "sophgo,cv1800-rtcsys-core", "syscon";
> +			reg = <0x05026000 0x1000>;
> +		};
> +
> +		soc-reset {
> +			compatible = "sophgo,cv1800-reset";
> +			sophgo,rtcsys-ctrl = <&rtcsys_ctrl>;
> +			sophgo,rtcsys-core = <&rtcsys_core>;
> +		};

I think these node is not suitable for riscv. It should use SBI SRST
extension to restart.

Regards,
Inochi

Re: [PATCH 08/10] riscv/arm64: dts: cv18xx: Add sysctl and reset nodes

[Alexander Sverdlin]

Thanks for quick feedback Inochi!

On Mon, 2025-02-10 at 13:13 +0800, Inochi Amaoto wrote:
> On Sun, Feb 09, 2025 at 11:06:33PM +0100, Alexander Sverdlin wrote:
> > Add reset controller node and required sysctl nodes.
> > 
> > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> > ---
> >   arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++
> >   1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > index 53834b0658b2..d793b6db4ed1 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 {
> >   			snps,data-width = <4>;
> >   			status = "disabled";
> >   		};
> > +
> 
> > +		rtcsys_ctrl: syscon@5025000 {
> > +			compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon";
> > +			reg = <0x05025000 0x1000>;
> > +		};
> > +
> > +		rtcsys_core: syscon@5026000 {
> > +			compatible = "sophgo,cv1800-rtcsys-core", "syscon";
> > +			reg = <0x05026000 0x1000>;
> > +		};
> > +
> > +		soc-reset {
> > +			compatible = "sophgo,cv1800-reset";
> > +			sophgo,rtcsys-ctrl = <&rtcsys_ctrl>;
> > +			sophgo,rtcsys-core = <&rtcsys_core>;
> > +		};
> 
> I think these node is not suitable for riscv. It should use SBI SRST
> extension to restart.

Independent from the particular form, or its correctness, this is still HW
description, right? It would be a "policy" for the kernel configuration, if
the particular build would rely on the FW or a kernel driver to reboot.

In other words, the HW block remains in place, no matter if it's controlled
by a kernel module or a FW. What the point in hiding it from the RiscV part
of DT, keeping on ARM64 side only?

-- 
Alexander Sverdlin.

Re: [PATCH 08/10] riscv/arm64: dts: cv18xx: Add sysctl and reset nodes

[Inochi Amaoto]

On Mon, Feb 10, 2025 at 12:47:59PM +0100, Alexander Sverdlin wrote:
> Thanks for quick feedback Inochi!
> 
> On Mon, 2025-02-10 at 13:13 +0800, Inochi Amaoto wrote:
> > On Sun, Feb 09, 2025 at 11:06:33PM +0100, Alexander Sverdlin wrote:
> > > Add reset controller node and required sysctl nodes.
> > > 
> > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> > > ---
> > >   arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++
> > >   1 file changed, 16 insertions(+)
> > > 
> > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > > index 53834b0658b2..d793b6db4ed1 100644
> > > --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> > > @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 {
> > >   			snps,data-width = <4>;
> > >   			status = "disabled";
> > >   		};
> > > +
> > 
> > > +		rtcsys_ctrl: syscon@5025000 {
> > > +			compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon";
> > > +			reg = <0x05025000 0x1000>;
> > > +		};
> > > +
> > > +		rtcsys_core: syscon@5026000 {
> > > +			compatible = "sophgo,cv1800-rtcsys-core", "syscon";
> > > +			reg = <0x05026000 0x1000>;
> > > +		};
> > > +
> > > +		soc-reset {
> > > +			compatible = "sophgo,cv1800-reset";
> > > +			sophgo,rtcsys-ctrl = <&rtcsys_ctrl>;
> > > +			sophgo,rtcsys-core = <&rtcsys_core>;
> > > +		};
> > 
> > I think these node is not suitable for riscv. It should use SBI SRST
> > extension to restart.
> 
> Independent from the particular form, or its correctness, this is still HW
> description, right? It would be a "policy" for the kernel configuration, if
> the particular build would rely on the FW or a kernel driver to reboot.
> 
> In other words, the HW block remains in place, no matter if it's controlled
> by a kernel module or a FW. What the point in hiding it from the RiscV part
> of DT, keeping on ARM64 side only?
> 

Yeah, I have make a mistake, the device is needed. SBI need these
device definition to handle some power event.

Regards,
Inochi

Re: [PATCH 08/10] riscv/arm64: dts: cv18xx: Add sysctl and reset nodes

[Krzysztof Kozlowski]

On 09/02/2025 23:06, Alexander Sverdlin wrote:
> Add reset controller node and required sysctl nodes.
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> index 53834b0658b2..d793b6db4ed1 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 {
>  			snps,data-width = <4>;
>  			status = "disabled";
>  		};
> +
> +		rtcsys_ctrl: syscon@5025000 {
> +			compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon";
> +			reg = <0x05025000 0x1000>;
> +		};
> +
> +		rtcsys_core: syscon@5026000 {
> +			compatible = "sophgo,cv1800-rtcsys-core", "syscon";
> +			reg = <0x05026000 0x1000>;
> +		};
> +
> +		soc-reset {
> +			compatible = "sophgo,cv1800-reset";

Nope. You cannot have non-MMIO nodes in SoC which proves this is not a
real SoC device. Neither compatible, nor its placement is correct.

Depending on the hardware design, this most likely is just part of your
5025000 block.


Best regards,
Krzysztof

[PATCH 09/10] power: reset: cv18xx: New driver

[Alexander Sverdlin]

Add new driver to support cold and warm reset on Cvitek CV18xx and Sophgo
SG2000 SoCs.

Link: https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 MAINTAINERS                        |  1 +
 drivers/power/reset/Kconfig        | 12 ++++
 drivers/power/reset/Makefile       |  1 +
 drivers/power/reset/cv18xx-reset.c | 89 ++++++++++++++++++++++++++++++
 4 files changed, 103 insertions(+)
 create mode 100644 drivers/power/reset/cv18xx-reset.c

diff --git a/MAINTAINERS b/MAINTAINERS
index e4f5d8f68581..b7fec02f7673 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22147,6 +22147,7 @@ M:	Chen Wang <unicorn_wang@outlook.com>
 M:	Inochi Amaoto <inochiama@outlook.com>
 T:	git https://github.com/sophgo/linux.git
 S:	Maintained
+F:	drivers/power/reset/cv18xx-reset.c
 N:	sophgo
 K:	sophgo
 
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 60bf0ca64cf3..d41ed3c2a30d 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -75,6 +75,18 @@ config POWER_RESET_BRCMSTB
 	  Say Y here if you have a Broadcom STB board and you wish
 	  to have restart support.
 
+config POWER_RESET_CV18XX
+	bool "Cvitek CV18XX/Sophgo SG2000 reset driver"
+	depends on ARCH_SOPHGO || COMPILE_TEST
+	depends on MFD_SYSCON
+	default ARCH_SOPHGO
+	help
+	  This driver provides restart support for Cvitek CV18xx and
+	  Sophgo SG2000 SoCs.
+
+	  Say Y here if you have a Cvitek CV18xx or Sophgo SG2000 SoC and
+	  you wish to have restart support.
+
 config POWER_RESET_EP93XX
 	bool "Cirrus EP93XX reset driver" if COMPILE_TEST
 	depends on MFD_SYSCON
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 10782d32e1da..ce24e74e0477 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_POWER_RESET_ATC260X) += atc260x-poweroff.o
 obj-$(CONFIG_POWER_RESET_AXXIA) += axxia-reset.o
 obj-$(CONFIG_POWER_RESET_BRCMKONA) += brcm-kona-reset.o
 obj-$(CONFIG_POWER_RESET_BRCMSTB) += brcmstb-reboot.o
+obj-$(CONFIG_POWER_RESET_CV18XX) += cv18xx-reset.o
 obj-$(CONFIG_POWER_RESET_EP93XX) += ep93xx-restart.o
 obj-$(CONFIG_POWER_RESET_GEMINI_POWEROFF) += gemini-poweroff.o
 obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
diff --git a/drivers/power/reset/cv18xx-reset.c b/drivers/power/reset/cv18xx-reset.c
new file mode 100644
index 000000000000..bc1797e7d3f5
--- /dev/null
+++ b/drivers/power/reset/cv18xx-reset.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/notifier.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+/* RTCSYS_CTRL registers */
+#define RTC_CTRL_UNLOCKKEY		0x04
+#define RTC_CTRL0			0x08
+#define  REQ_PWR_CYC			BIT(3)
+#define  REQ_WARM_RST			BIT(4)
+
+/* RTCSYS_CORE registers */
+#define RTC_EN_PWR_CYC_REQ		0xC8
+#define RTC_EN_WARM_RST_REQ		0xCC
+
+static struct regmap *rtcsys_ctrl_regs;
+static struct regmap *rtcsys_core_regs;
+
+static int cv18xx_restart_handler(struct sys_off_data *data)
+{
+	u32 reg_en = RTC_EN_WARM_RST_REQ;
+	u32 request = 0xFFFF0800;
+
+	if (data->mode == REBOOT_COLD) {
+		reg_en = RTC_EN_PWR_CYC_REQ;
+		request |= REQ_PWR_CYC;
+	} else {
+		request |= REQ_WARM_RST;
+	}
+
+	/* Enable reset request */
+	regmap_write(rtcsys_core_regs, reg_en, 1);
+	/* Enable CTRL0 register access */
+	regmap_write(rtcsys_ctrl_regs, RTC_CTRL_UNLOCKKEY, 0xAB18);
+	/* Request reset */
+	regmap_write(rtcsys_ctrl_regs, RTC_CTRL0, request);
+
+	return NOTIFY_DONE;
+}
+
+static int cv18xx_reset_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	if (!np)
+		return -ENODEV;
+
+	rtcsys_ctrl_regs = syscon_regmap_lookup_by_phandle(np, "sophgo,rtcsys-ctrl");
+	if (IS_ERR(rtcsys_ctrl_regs))
+		return dev_err_probe(dev, PTR_ERR(rtcsys_ctrl_regs),
+				     "sophgo,rtcsys-ctrl lookup failed\n");
+
+	rtcsys_core_regs = syscon_regmap_lookup_by_phandle(np, "sophgo,rtcsys-core");
+	if (IS_ERR(rtcsys_core_regs))
+		return dev_err_probe(dev, PTR_ERR(rtcsys_core_regs),
+				     "sophgo,rtcsys-core lookup failed\n");
+
+	ret = devm_register_restart_handler(&pdev->dev, cv18xx_restart_handler, NULL);
+	if (ret)
+		dev_err(&pdev->dev, "Cannot register restart handler (%pe)\n", ERR_PTR(ret));
+	return ret;
+}
+
+static const struct of_device_id cv18xx_reset_of_match[] = {
+	{ .compatible = "sophgo,cv1800-reset" },
+	{}
+};
+MODULE_DEVICE_TABLE(platform, cv18xx_reset_of_match);
+
+static struct platform_driver cv18xx_reset_driver = {
+	.probe = cv18xx_reset_probe,
+	.driver = {
+		.name = "cv18xx-reset",
+		.of_match_table = cv18xx_reset_of_match,
+	},
+};
+module_platform_driver(cv18xx_reset_driver);
+
+MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>");
+MODULE_DESCRIPTION("Cvitek CV18xx/Sophgo SG2000 Reset Driver");
+MODULE_ALIAS("platform:cv18xx-reset");
-- 
2.48.1

Re: [PATCH 09/10] power: reset: cv18xx: New driver

[Krzysztof Kozlowski]

On 09/02/2025 23:06, Alexander Sverdlin wrote:
> +
> +static int cv18xx_reset_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	int ret;
> +
> +	if (!np)
> +		return -ENODEV;
> +
> +	rtcsys_ctrl_regs = syscon_regmap_lookup_by_phandle(np, "sophgo,rtcsys-ctrl");
> +	if (IS_ERR(rtcsys_ctrl_regs))
> +		return dev_err_probe(dev, PTR_ERR(rtcsys_ctrl_regs),
> +				     "sophgo,rtcsys-ctrl lookup failed\n");
> +
> +	rtcsys_core_regs = syscon_regmap_lookup_by_phandle(np, "sophgo,rtcsys-core");
> +	if (IS_ERR(rtcsys_core_regs))
> +		return dev_err_probe(dev, PTR_ERR(rtcsys_core_regs),
> +				     "sophgo,rtcsys-core lookup failed\n");
> +
> +	ret = devm_register_restart_handler(&pdev->dev, cv18xx_restart_handler, NULL);
> +	if (ret)
> +		dev_err(&pdev->dev, "Cannot register restart handler (%pe)\n", ERR_PTR(ret));

You called it reset driver and placed it in reset, but this is reboot
handler?

> +	return ret;
> +}
> +
> +static const struct of_device_id cv18xx_reset_of_match[] = {
> +	{ .compatible = "sophgo,cv1800-reset" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(platform, cv18xx_reset_of_match);
> +
> +static struct platform_driver cv18xx_reset_driver = {
> +	.probe = cv18xx_reset_probe,
> +	.driver = {
> +		.name = "cv18xx-reset",
> +		.of_match_table = cv18xx_reset_of_match,
> +	},
> +};
> +module_platform_driver(cv18xx_reset_driver);
> +
> +MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>");
> +MODULE_DESCRIPTION("Cvitek CV18xx/Sophgo SG2000 Reset Driver");
> +MODULE_ALIAS("platform:cv18xx-reset");

You should not need MODULE_ALIAS() in normal cases. If you need it,
usually it means your device ID table is wrong (e.g. misses either
entries or MODULE_DEVICE_TABLE()). MODULE_ALIAS() is not a substitute
for incomplete ID table.




Best regards,
Krzysztof

[PATCH 10/10] arm64: defconfig: Enable rudimentary Sophgo SG2000 support

[Alexander Sverdlin]

Enable ARCH_SOPHGO, pinctrl (built-in, required to boot), ADC as module.
This defconfig is able to boot from SD card on Milk-V Duo Module 01 EVB.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
 arch/arm64/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index cb7da4415599..56e2c833f745 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -66,6 +66,7 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARCH_SEATTLE=y
 CONFIG_ARCH_INTEL_SOCFPGA=y
+CONFIG_ARCH_SOPHGO=y
 CONFIG_ARCH_STM32=y
 CONFIG_ARCH_SYNQUACER=y
 CONFIG_ARCH_TEGRA=y
@@ -650,6 +651,7 @@ CONFIG_PINCTRL_SM8450_LPASS_LPI=m
 CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
 CONFIG_PINCTRL_SM8550_LPASS_LPI=m
 CONFIG_PINCTRL_SM8650_LPASS_LPI=m
+CONFIG_PINCTRL_SOPHGO_SG2000=y
 CONFIG_GPIO_ALTERA=m
 CONFIG_GPIO_DAVINCI=y
 CONFIG_GPIO_DWAPB=y
@@ -1517,6 +1519,7 @@ CONFIG_QCOM_SPMI_VADC=m
 CONFIG_QCOM_SPMI_ADC5=m
 CONFIG_ROCKCHIP_SARADC=m
 CONFIG_RZG2L_ADC=m
+CONFIG_SOPHGO_CV1800B_ADC=m
 CONFIG_TI_ADS1015=m
 CONFIG_TI_AM335X_ADC=m
 CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-- 
2.48.1

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Chen Wang]

On 2025/2/10 6:06, Alexander Sverdlin wrote:
> This series adds very basic support for Milk-V Duo Module 01 EVB [1] in
> arm64 mode. The SoC (SG2000) is dual-arch, RiscV and ARM64, the latter has
> been chosen because the upstream toolchain can be utilized.
>
> Sophgo SG2000 seems to be a continuation of the Cvitek CV18xx series, same
> peripherals with an addition of ARM64 core. Therefore it would be
> beneficial not to copy-paste the peripherals' device-tree, but rather split
> the most suitable riscv DT into ARCH-specific and peripherals parts and
> just include the latter on the arm64 side.
>
> This series adds the device-tree for Milk-V Duo Module 01 EVB, which
> in turn contains Milk-V Duo Module 01 (separate .dtsi) on it, which has
> SG2000 SoC inside (separate .dtsi).
>
> This series has been tested with Sophgo-provided U-Boot binary [2]: it
> boots from SD card, pinctrl, serial, GPIO drivers are functional (same
> as for RiscV-based CV18xx SoCs).
> New reset driver is provided as an alternative to the ATF PSCI handler,
> which Sophgo only provides in binary form.

I just see Inochi posted a patchset about cv18xx reset driver [1]. FYI.

Maybe you and Inochi need to communicate with each other and synchronize 
the related work in this regard.

Link: 
https://lore.kernel.org/linux-riscv/20250209122936.2338821-1-inochiama@gmail.com/ 
[1]

>
> Partial SoC documentation is available [3].
>
> This series lacks the support of:
> - USB
> - Audio
> - Ethernet
> - WiFi
> - Bluetooth
> - eMMC
> - Video
>
> It would probably make sense that the whole series would go into SOC tree,
> even though technically nothing prevents the reboot/reset driver to come
> in PM/reset tree. If everything would come together, `reboot` command would
> work out of the box.
>
> [1] https://milkv.io/docs/duo/getting-started/duo-module-01
> [2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
> [3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
>
> Alexander Sverdlin (10):
>    arm64: Add SOPHGO SOC family Kconfig support
>    riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts
>    arm64: dts: sophgo: Add initial SG2000 SoC device tree
>    arm64: dts: sophgo: Add Duo Module 01
>    arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
>    dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl
>      compatible
>    dt-bindings: reset: sophgo: Add CV18xx reset controller
>    riscv/arm64: dts: cv18xx: Add sysctl and reset nodes
>    power: reset: cv18xx: New driver
>    arm64: defconfig: Enable rudimentary Sophgo SG2000 support
>
>   .../devicetree/bindings/mfd/syscon.yaml       |   4 +
>   .../bindings/reset/sophgo,cv1800-reset.yaml   |  38 ++
>   MAINTAINERS                                   |   1 +
>   arch/arm64/Kconfig.platforms                  |  12 +
>   arch/arm64/boot/dts/Makefile                  |   1 +
>   arch/arm64/boot/dts/sophgo/Makefile           |   2 +
>   arch/arm64/boot/dts/sophgo/sg2000.dtsi        |  79 +++++
>   .../sophgo/sg2000_milkv_duo_module_01.dtsi    |  84 +++++
>   .../sophgo/sg2000_milkv_duo_module_01_evb.dts |  30 ++
>   arch/arm64/configs/defconfig                  |   3 +
>   arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
>   arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 329 ++++++++++++++++++
>   arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +---------------
>   drivers/power/reset/Kconfig                   |  12 +
>   drivers/power/reset/Makefile                  |   1 +
>   drivers/power/reset/cv18xx-reset.c            |  89 +++++
>   16 files changed, 689 insertions(+), 303 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
>   create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
>   create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
>   create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
>   create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts
>   create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
>   create mode 100644 drivers/power/reset/cv18xx-reset.c
>

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Inochi Amaoto]

On Mon, Feb 10, 2025 at 08:02:12AM +0800, Chen Wang wrote:
> 
> On 2025/2/10 6:06, Alexander Sverdlin wrote:
> > This series adds very basic support for Milk-V Duo Module 01 EVB [1] in
> > arm64 mode. The SoC (SG2000) is dual-arch, RiscV and ARM64, the latter has
> > been chosen because the upstream toolchain can be utilized.
> > 
> > Sophgo SG2000 seems to be a continuation of the Cvitek CV18xx series, same
> > peripherals with an addition of ARM64 core. Therefore it would be
> > beneficial not to copy-paste the peripherals' device-tree, but rather split
> > the most suitable riscv DT into ARCH-specific and peripherals parts and
> > just include the latter on the arm64 side.
> > 
> > This series adds the device-tree for Milk-V Duo Module 01 EVB, which
> > in turn contains Milk-V Duo Module 01 (separate .dtsi) on it, which has
> > SG2000 SoC inside (separate .dtsi).
> > 
> > This series has been tested with Sophgo-provided U-Boot binary [2]: it
> > boots from SD card, pinctrl, serial, GPIO drivers are functional (same
> > as for RiscV-based CV18xx SoCs).
> > New reset driver is provided as an alternative to the ATF PSCI handler,
> > which Sophgo only provides in binary form.
> 
> I just see Inochi posted a patchset about cv18xx reset driver [1]. FYI.
> 
> Maybe you and Inochi need to communicate with each other and synchronize the
> related work in this regard.
> 
> Link: https://lore.kernel.org/linux-riscv/20250209122936.2338821-1-inochiama@gmail.com/
> [1]
> 

It is a power restart device, not the reset controller, I suggests you change
the device name.

> > 
> > Partial SoC documentation is available [3].
> > 
> > This series lacks the support of:
> > - USB
> > - Audio
> > - Ethernet
> > - WiFi
> > - Bluetooth
> > - eMMC
> > - Video
> > 
> > It would probably make sense that the whole series would go into SOC tree,
> > even though technically nothing prevents the reboot/reset driver to come
> > in PM/reset tree. If everything would come together, `reboot` command would
> > work out of the box.
> > 
> > [1] https://milkv.io/docs/duo/getting-started/duo-module-01
> > [2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
> > [3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> > 
> > Alexander Sverdlin (10):
> >    arm64: Add SOPHGO SOC family Kconfig support
> >    riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts
> >    arm64: dts: sophgo: Add initial SG2000 SoC device tree
> >    arm64: dts: sophgo: Add Duo Module 01
> >    arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
> >    dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl
> >      compatible
> >    dt-bindings: reset: sophgo: Add CV18xx reset controller
> >    riscv/arm64: dts: cv18xx: Add sysctl and reset nodes
> >    power: reset: cv18xx: New driver
> >    arm64: defconfig: Enable rudimentary Sophgo SG2000 support
> > 
> >   .../devicetree/bindings/mfd/syscon.yaml       |   4 +
> >   .../bindings/reset/sophgo,cv1800-reset.yaml   |  38 ++
> >   MAINTAINERS                                   |   1 +
> >   arch/arm64/Kconfig.platforms                  |  12 +
> >   arch/arm64/boot/dts/Makefile                  |   1 +
> >   arch/arm64/boot/dts/sophgo/Makefile           |   2 +
> >   arch/arm64/boot/dts/sophgo/sg2000.dtsi        |  79 +++++
> >   .../sophgo/sg2000_milkv_duo_module_01.dtsi    |  84 +++++
> >   .../sophgo/sg2000_milkv_duo_module_01_evb.dts |  30 ++
> >   arch/arm64/configs/defconfig                  |   3 +
> >   arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
> >   arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 329 ++++++++++++++++++
> >   arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +---------------
> >   drivers/power/reset/Kconfig                   |  12 +
> >   drivers/power/reset/Makefile                  |   1 +
> >   drivers/power/reset/cv18xx-reset.c            |  89 +++++
> >   16 files changed, 689 insertions(+), 303 deletions(-)
> >   create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
> >   create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
> >   create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
> >   create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
> >   create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts
> >   create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
> >   create mode 100644 drivers/power/reset/cv18xx-reset.c
> > 

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Inochi Amaoto]

> It would probably make sense that the whole series would go into SOC tree,
> even though technically nothing prevents the reboot/reset driver to come
> in PM/reset tree. If everything would come together, `reboot` command would
> work out of the box.
> 
> [1] https://milkv.io/docs/duo/getting-started/duo-module-01
> [2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
> [3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> 

This reboot implentment across the RTC and 8051 domain, which is
still a big problem to be upstreamed. This should be designed 
carefully and needs further discussion. Adding these two syscon
compatiable may be not a good idea and cause some problem. I invite
Yixun to this talk and he may give some useful suggestions.

At last, I prefer this goes to an separate patch series, and
implement with rtc device.

Regards,
Inochi

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Alexander Sverdlin]

Thanks for quick feedback Inochi!

On Mon, 2025-02-10 at 13:33 +0800, Inochi Amaoto wrote:
> > It would probably make sense that the whole series would go into SOC tree,
> > even though technically nothing prevents the reboot/reset driver to come
> > in PM/reset tree. If everything would come together, `reboot` command would
> > work out of the box.
> > 
> > [1] https://milkv.io/docs/duo/getting-started/duo-module-01
> > [2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
> > [3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> > 
> 
> This reboot implentment across the RTC and 8051 domain, which is
> still a big problem to be upstreamed. This should be designed 

Could you please elaborate on the "big problem"?
Does the binary-distributed ATF perform some other type of reset in WARM case?
(COLD is just mirorred based on TRM).

> carefully and needs further discussion. Adding these two syscon
> compatiable may be not a good idea and cause some problem. I invite
> Yixun to this talk and he may give some useful suggestions.
> 
> At last, I prefer this goes to an separate patch series, and
> implement with rtc device.

Sure, I can split the reboot story from the series...

-- 
Alexander Sverdlin.

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Alexander Sverdlin]

Hi Inochi!

On Mon, 2025-02-10 at 13:33 +0800, Inochi Amaoto wrote:
> > It would probably make sense that the whole series would go into SOC tree,
> > even though technically nothing prevents the reboot/reset driver to come
> > in PM/reset tree. If everything would come together, `reboot` command would
> > work out of the box.
> > 
> > [1] https://milkv.io/docs/duo/getting-started/duo-module-01
> > [2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
> > [3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> > 
> 
> This reboot implentment across the RTC and 8051 domain, which is
> still a big problem to be upstreamed. This should be designed 

Now I've got it. The problem is not in the reboot procedure, but
rather how to model this thing in the DT, because of all these
unrelated functions brought into two HW address spaces...

> carefully and needs further discussion. Adding these two syscon
> compatiable may be not a good idea and cause some problem. I invite
> Yixun to this talk and he may give some useful suggestions.
> 
> At last, I prefer this goes to an separate patch series, and
> implement with rtc device.

-- 
Alexander Sverdlin.

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Alexander Sverdlin]

Hi Inochi!

On Mon, 2025-02-10 at 21:55 +0100, Alexander Sverdlin wrote:
> > > It would probably make sense that the whole series would go into SOC tree,
> > > even though technically nothing prevents the reboot/reset driver to come
> > > in PM/reset tree. If everything would come together, `reboot` command would
> > > work out of the box.
> > > 
> > > [1] https://milkv.io/docs/duo/getting-started/duo-module-01
> > > [2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
> > > [3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> > > 
> > 
> > This reboot implentment across the RTC and 8051 domain, which is
> > still a big problem to be upstreamed. This should be designed 
> 
> Now I've got it. The problem is not in the reboot procedure, but
> rather how to model this thing in the DT, because of all these
> unrelated functions brought into two HW address spaces...
> 
> > carefully and needs further discussion. Adding these two syscon
> > compatiable may be not a good idea and cause some problem. I invite
> > Yixun to this talk and he may give some useful suggestions.
> > 
> > At last, I prefer this goes to an separate patch series, and
> > implement with rtc device.

Thanks for your hints!
I've completely missed the RTC driver in progress [1].
I will provide a patch registering the reboot handler on top of the driver
as soon as it's accepted.

[1] https://patchwork.ozlabs.org/project/rtc-linux/patch/20240428060848.706573-3-qiujingbao.dlmu@gmail.com/

-- 
Alexander Sverdlin.

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Inochi Amaoto]

On Tue, Feb 11, 2025 at 08:37:01PM +0100, Alexander Sverdlin wrote:
> Hi Inochi!
> 
> On Mon, 2025-02-10 at 21:55 +0100, Alexander Sverdlin wrote:
> > > > It would probably make sense that the whole series would go into SOC tree,
> > > > even though technically nothing prevents the reboot/reset driver to come
> > > > in PM/reset tree. If everything would come together, `reboot` command would
> > > > work out of the box.
> > > > 
> > > > [1] https://milkv.io/docs/duo/getting-started/duo-module-01
> > > > [2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
> > > > [3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> > > > 
> > > 
> > > This reboot implentment across the RTC and 8051 domain, which is
> > > still a big problem to be upstreamed. This should be designed 
> > 
> > Now I've got it. The problem is not in the reboot procedure, but
> > rather how to model this thing in the DT, because of all these
> > unrelated functions brought into two HW address spaces...
> > 
> > > carefully and needs further discussion. Adding these two syscon
> > > compatiable may be not a good idea and cause some problem. I invite
> > > Yixun to this talk and he may give some useful suggestions.
> > > 
> > > At last, I prefer this goes to an separate patch series, and
> > > implement with rtc device.
> 
> Thanks for your hints!
> I've completely missed the RTC driver in progress [1].
> I will provide a patch registering the reboot handler on top of the driver
> as soon as it's accepted.
> 
> [1] https://patchwork.ozlabs.org/project/rtc-linux/patch/20240428060848.706573-3-qiujingbao.dlmu@gmail.com/
> 

As far as I know the RTC patch is no longer maintained. Maybe you can
pick it up?
The patch states can be found on:
https://github.com/sophgo/linux/wiki

Regards,
Inochi

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Alexander Sverdlin]

Hi Inochi!

On Wed, 2025-02-12 at 08:29 +0800, Inochi Amaoto wrote:
> > Thanks for your hints!
> > I've completely missed the RTC driver in progress [1].
> > I will provide a patch registering the reboot handler on top of the driver
> > as soon as it's accepted.
> > 
> > [1] https://patchwork.ozlabs.org/project/rtc-linux/patch/20240428060848.706573-3-qiujingbao.dlmu@gmail.com/
> > 
> 
> As far as I know the RTC patch is no longer maintained. Maybe you can
> pick it up?

I can try... If only I can make it work...

> The patch states can be found on:
> https://github.com/sophgo/linux/wiki

Thanks for the link!

-- 
Alexander Sverdlin.

Re: [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB

[Rob Herring (Arm)]

On Sun, 09 Feb 2025 23:06:25 +0100, Alexander Sverdlin wrote:
> This series adds very basic support for Milk-V Duo Module 01 EVB [1] in
> arm64 mode. The SoC (SG2000) is dual-arch, RiscV and ARM64, the latter has
> been chosen because the upstream toolchain can be utilized.
> 
> Sophgo SG2000 seems to be a continuation of the Cvitek CV18xx series, same
> peripherals with an addition of ARM64 core. Therefore it would be
> beneficial not to copy-paste the peripherals' device-tree, but rather split
> the most suitable riscv DT into ARCH-specific and peripherals parts and
> just include the latter on the arm64 side.
> 
> This series adds the device-tree for Milk-V Duo Module 01 EVB, which
> in turn contains Milk-V Duo Module 01 (separate .dtsi) on it, which has
> SG2000 SoC inside (separate .dtsi).
> 
> This series has been tested with Sophgo-provided U-Boot binary [2]: it
> boots from SD card, pinctrl, serial, GPIO drivers are functional (same
> as for RiscV-based CV18xx SoCs).
> New reset driver is provided as an alternative to the ATF PSCI handler,
> which Sophgo only provides in binary form.
> 
> Partial SoC documentation is available [3].
> 
> This series lacks the support of:
> - USB
> - Audio
> - Ethernet
> - WiFi
> - Bluetooth
> - eMMC
> - Video
> 
> It would probably make sense that the whole series would go into SOC tree,
> even though technically nothing prevents the reboot/reset driver to come
> in PM/reset tree. If everything would come together, `reboot` command would
> work out of the box.
> 
> [1] https://milkv.io/docs/duo/getting-started/duo-module-01
> [2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
> [3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
> 
> Alexander Sverdlin (10):
>   arm64: Add SOPHGO SOC family Kconfig support
>   riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts
>   arm64: dts: sophgo: Add initial SG2000 SoC device tree
>   arm64: dts: sophgo: Add Duo Module 01
>   arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
>   dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl
>     compatible
>   dt-bindings: reset: sophgo: Add CV18xx reset controller
>   riscv/arm64: dts: cv18xx: Add sysctl and reset nodes
>   power: reset: cv18xx: New driver
>   arm64: defconfig: Enable rudimentary Sophgo SG2000 support
> 
>  .../devicetree/bindings/mfd/syscon.yaml       |   4 +
>  .../bindings/reset/sophgo,cv1800-reset.yaml   |  38 ++
>  MAINTAINERS                                   |   1 +
>  arch/arm64/Kconfig.platforms                  |  12 +
>  arch/arm64/boot/dts/Makefile                  |   1 +
>  arch/arm64/boot/dts/sophgo/Makefile           |   2 +
>  arch/arm64/boot/dts/sophgo/sg2000.dtsi        |  79 +++++
>  .../sophgo/sg2000_milkv_duo_module_01.dtsi    |  84 +++++
>  .../sophgo/sg2000_milkv_duo_module_01_evb.dts |  30 ++
>  arch/arm64/configs/defconfig                  |   3 +
>  arch/riscv/boot/dts/sophgo/cv181x.dtsi        |   2 +-
>  arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 329 ++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 305 +---------------
>  drivers/power/reset/Kconfig                   |  12 +
>  drivers/power/reset/Makefile                  |   1 +
>  drivers/power/reset/cv18xx-reset.c            |  89 +++++
>  16 files changed, 689 insertions(+), 303 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml
>  create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
>  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
>  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi
>  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
>  create mode 100644 drivers/power/reset/cv18xx-reset.c
> 
> --
> 2.48.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/sophgo/' for 20250209220646.1090868-1-alexander.sverdlin@gmail.com:

arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dtb: /: failed to match any schema with compatible: ['sophgo,sg2000']
arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dtb: soc: soc-reset: 'ranges' is a required property
	from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dtb: l2-cache: 'cache-unified' is a dependency of 'cache-size'
	from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dtb: l2-cache: 'cache-unified' is a required property
	from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dtb: l2-cache: Unevaluated properties are not allowed ('cache-level', 'cache-size' were unexpected)
	from schema $id: http://devicetree.org/schemas/cache.yaml#