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Fri, 08 Aug 2025 16:58:44 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A8D2340046; Fri, 8 Aug 2025 16:57:20 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D7F79727648; Fri, 8 Aug 2025 16:55:57 +0200 (CEST) Received: from [10.130.77.120] (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 8 Aug 2025 16:55:54 +0200 Message-ID: Date: Fri, 8 Aug 2025 16:55:52 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Christian Bruel Subject: Re: [PATCH v12 2/9] PCI: stm32: Add PCIe host support for STM32MP25 To: Bjorn Helgaas , Linus Walleij CC: , , , , , , , , , , , , , , , , , , , References: <20250807180951.GA56737@bhelgaas> Content-Language: en-US In-Reply-To: <20250807180951.GA56737@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.130.77.120] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_04,2025-08-06_01,2025-03-28_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250808_075900_087877_B5D72612 X-CRM114-Status: GOOD ( 12.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/7/25 20:09, Bjorn Helgaas wrote: > [+to Linus for pinctrl usage question below] > > On Tue, Jun 10, 2025 at 11:07:07AM +0200, Christian Bruel wrote: >> Add driver for the STM32MP25 SoC PCIe Gen1 2.5 GT/s and Gen2 5GT/s >> controller based on the DesignWare PCIe core. >> >> + >> + return pinctrl_pm_select_sleep_state(dev); > > Isn't there some setup required before we can use > pinctrl_select_state(), pinctrl_pm_select_sleep_state(), > pinctrl_pm_select_default_state(), etc? > > I expected something like devm_pinctrl_get() in the .probe() path, but > I don't see anything. I don't know how pinctrl works, but I don't see > how dev->pins gets set up. Linus knows better, but the dev->pins states are attached to the dev struct before probe by the pinctrl driver /** * pinctrl_bind_pins() - called by the device core before probe * @dev: the device that is just about to probe */ int pinctrl_bind_pins(struct device *dev) Christian