Re: [PATCH 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC

[Krzysztof Kozlowski <krzk@kernel.org>]

On 15/08/2025 15:18, Yuanfang Zhang wrote:
> Add device tree binding for Qualcomm Coresight Interconnect Trace
> Netwrok On Chip (ITNOC). This TNOC acts as a CoreSight
> graph link that forwards trace data from a subsystem to the
> Aggregator TNOC, without aggregation or ATID functionality.
> 
> Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
> ---
>  .../bindings/arm/qcom,coresight-itnoc.yaml         | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..fd224e07ce68918b453210763aacda585d5a5ca2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Interconnect Trace Network On Chip - ITNOC
> +
> +maintainers:
> +  - Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  The Interconnect TNOC is a CoreSight graph link that forwards trace data
> +  from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it
> +  does not have aggregation and ATID functionality.
> +
> +select:
> +  properties:
> +    compatible:
> +      contains:
> +        enum:
> +          - qcom,coresight-itnoc
> +  required:
> +    - compatible

Why all this? Drop

> +
> +properties:
> +  $nodename:
> +    pattern: "^tnoc(@[0-9a-f]+)?$"

Why are you requiring a non-generic name?

> +
> +  compatible:
> +    items:

No need for items

> +      - const: qcom,coresight-itnoc
> +
> +  reg:
> +    maxItems: 1
> +    description: Base address and size of the ITNOC registers.

Drop, redundant

> +
> +  clock-names:
> +    items:
> +      - const: apb

Drop clock-names, obvious. Also, odd order - names are never before
actual property.

> +
> +  clocks:
> +    maxItems: 1
> +
> +  in-ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      '#address-cells':
> +        const: 1
> +      '#size-cells':
> +        const: 0
> +
> +    patternProperties:
> +      '^port(@[0-9a-f]{1,2})?$':

Why do you have here 255 ports?

> +        description: Input connections from CoreSight Trace Bus
> +        $ref: /schemas/graph.yaml#/properties/port
> +    additionalProperties: false

This goes after $ref

> +
> +  out-ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port:
> +        description: out connections to aggregator TNOC
> +        $ref: /schemas/graph.yaml#/properties/port
> +    additionalProperties: false

This goes after ref

> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names

And here different order... Be consistent. See also DTS coding style.

> +  - in-ports
> +  - out-ports
> +
> +additionalProperties: false
> +



Best regards,
Krzysztof