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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Claudiu, On 11/03/24 11:28 am, claudiu beznea wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 23.02.2024 19:28, Varshini Rajendran wrote: >> Add a driver for the PMC clocks of sam9x7 Soc family. >> >> Signed-off-by: Varshini Rajendran >> --- >> Changes in v4: >> - Changed variable name alloc_mem to clk_mux_buffer to be more >> suggestive >> - Changed description of @f structure member appropriately >> --- >> drivers/clk/at91/Makefile | 1 + >> drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 947 insertions(+) >> create mode 100644 drivers/clk/at91/sam9x7.c >> >> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile >> index 89061b85e7d2..8e3684ba2c74 100644 >> --- a/drivers/clk/at91/Makefile >> +++ b/drivers/clk/at91/Makefile >> @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat. >> obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o >> obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o >> obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o >> +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o >> obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o >> obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o >> obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o >> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c >> new file mode 100644 >> index 000000000000..d03387d2e35a >> --- /dev/null >> +++ b/drivers/clk/at91/sam9x7.c >> @@ -0,0 +1,946 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * SAM9X7 PMC code. >> + * >> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries >> + * >> + * Author: Varshini Rajendran >> + * >> + */ >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> + >> +#include "pmc.h" >> + >> +static DEFINE_SPINLOCK(pmc_pll_lock); >> +static DEFINE_SPINLOCK(mck_lock); >> + >> +/** >> + * enum pll_ids - PLL clocks identifiers >> + * @PLL_ID_PLLA: PLLA identifier >> + * @PLL_ID_UPLL: UPLL identifier >> + * @PLL_ID_AUDIO: Audio PLL identifier >> + * @PLL_ID_LVDS: LVDS PLL identifier >> + * @PLL_ID_PLLA_DIV2: PLLA DIV2 identifier >> + * @PLL_ID_MAX: Max PLL Identifier >> + */ >> +enum pll_ids { >> + PLL_ID_PLLA, >> + PLL_ID_UPLL, >> + PLL_ID_AUDIO, >> + PLL_ID_LVDS, >> + PLL_ID_PLLA_DIV2, >> + PLL_ID_MAX, >> +}; >> + >> +/** >> + * enum pll_type - PLL type identifiers >> + * @PLL_TYPE_FRAC: fractional PLL identifier >> + * @PLL_TYPE_DIV: divider PLL identifier >> + */ >> +enum pll_type { >> + PLL_TYPE_FRAC, >> + PLL_TYPE_DIV, >> +}; >> + >> +static const struct clk_master_characteristics mck_characteristics = { >> + .output = { .min = 32000000, .max = 266666667 }, >> + .divisors = { 1, 2, 4, 3, 5}, >> + .have_div3_pres = 1, >> +}; >> + >> +static const struct clk_master_layout sam9x7_master_layout = { >> + .mask = 0x373, >> + .pres_shift = 4, >> + .offset = 0x28, >> +}; >> + >> +/* Fractional PLL core output range. */ >> +static const struct clk_range plla_core_outputs[] = { >> + { .min = 375000000, .max = 1600000000 }, >> +}; >> + >> +static const struct clk_range upll_core_outputs[] = { >> + { .min = 600000000, .max = 1200000000 }, >> +}; >> + >> +static const struct clk_range lvdspll_core_outputs[] = { >> + { .min = 400000000, .max = 800000000 }, >> +}; >> + >> +static const struct clk_range audiopll_core_outputs[] = { >> + { .min = 400000000, .max = 800000000 }, >> +}; >> + >> +static const struct clk_range plladiv2_core_outputs[] = { >> + { .min = 375000000, .max = 1600000000 }, >> +}; >> + >> +/* Fractional PLL output range. */ >> +static const struct clk_range plla_outputs[] = { >> + { .min = 732421, .max = 800000000 }, >> +}; >> + >> +static const struct clk_range upll_outputs[] = { >> + { .min = 300000000, .max = 600000000 }, >> +}; >> + >> +static const struct clk_range lvdspll_outputs[] = { >> + { .min = 10000000, .max = 800000000 }, >> +}; >> + >> +static const struct clk_range audiopll_outputs[] = { >> + { .min = 10000000, .max = 800000000 }, >> +}; >> + >> +static const struct clk_range plladiv2_outputs[] = { >> + { .min = 366210, .max = 400000000 }, >> +}; >> + >> +/* PLL characteristics. */ >> +static const struct clk_pll_characteristics plla_characteristics = { >> + .input = { .min = 20000000, .max = 50000000 }, >> + .num_output = ARRAY_SIZE(plla_outputs), >> + .output = plla_outputs, >> + .core_output = plla_core_outputs, >> +}; >> + >> +static const struct clk_pll_characteristics upll_characteristics = { >> + .input = { .min = 20000000, .max = 50000000 }, >> + .num_output = ARRAY_SIZE(upll_outputs), >> + .output = upll_outputs, >> + .core_output = upll_core_outputs, >> + .upll = true, >> +}; >> + >> +static const struct clk_pll_characteristics lvdspll_characteristics = { >> + .input = { .min = 20000000, .max = 50000000 }, >> + .num_output = ARRAY_SIZE(lvdspll_outputs), >> + .output = lvdspll_outputs, >> + .core_output = lvdspll_core_outputs, >> +}; >> + >> +static const struct clk_pll_characteristics audiopll_characteristics = { >> + .input = { .min = 20000000, .max = 50000000 }, >> + .num_output = ARRAY_SIZE(audiopll_outputs), >> + .output = audiopll_outputs, >> + .core_output = audiopll_core_outputs, >> +}; >> + >> +static const struct clk_pll_characteristics plladiv2_characteristics = { >> + .input = { .min = 20000000, .max = 50000000 }, >> + .num_output = ARRAY_SIZE(plladiv2_outputs), >> + .output = plladiv2_outputs, >> + .core_output = plladiv2_core_outputs, >> +}; >> + >> +/* Layout for fractional PLL ID PLLA. */ >> +static const struct clk_pll_layout plla_frac_layout = { >> + .mul_mask = GENMASK(31, 24), >> + .frac_mask = GENMASK(21, 0), >> + .mul_shift = 24, >> + .frac_shift = 0, >> + .div2 = 1, > > It seems to me that this is not taken into account (see below). > >> +}; >> + >> +/* Layout for fractional PLLs. */ >> +static const struct clk_pll_layout pll_frac_layout = { >> + .mul_mask = GENMASK(31, 24), >> + .frac_mask = GENMASK(21, 0), >> + .mul_shift = 24, >> + .frac_shift = 0, >> +}; >> + >> +/* Layout for DIV PLLs. */ >> +static const struct clk_pll_layout pll_divpmc_layout = { >> + .div_mask = GENMASK(7, 0), >> + .endiv_mask = BIT(29), >> + .div_shift = 0, >> + .endiv_shift = 29, >> +}; >> + >> +/* Layout for DIV PLL ID PLLADIV2. */ >> +static const struct clk_pll_layout plladiv2_divpmc_layout = { >> + .div_mask = GENMASK(7, 0), >> + .endiv_mask = BIT(29), >> + .div_shift = 0, >> + .endiv_shift = 29, >> + .div2 = 1, >> +}; >> + >> +/* Layout for DIVIO dividers. */ >> +static const struct clk_pll_layout pll_divio_layout = { >> + .div_mask = GENMASK(19, 12), >> + .endiv_mask = BIT(30), >> + .div_shift = 12, >> + .endiv_shift = 30, >> +}; >> + >> +/* >> + * PLL clocks description >> + * @n: clock name >> + * @p: clock parent >> + * @l: clock layout >> + * @t: clock type >> + * @c: pll characteristics >> + * @f: clock flags >> + * @eid: export index in sam9x7->chws[] array >> + */ >> +static const struct { >> + const char *n; >> + const char *p; >> + const struct clk_pll_layout *l; >> + u8 t; >> + const struct clk_pll_characteristics *c; >> + unsigned long f; >> + u8 eid; >> +} sam9x7_plls[][PLL_ID_MAX] = { >> + [PLL_ID_PLLA] = { >> + { >> + .n = "plla_fracck", >> + .p = "mainck", >> + .l = &plla_frac_layout, >> + .t = PLL_TYPE_FRAC, >> + /* >> + * This feeds plla_divpmcck which feeds CPU. It should >> + * not be disabled. >> + */ >> + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, >> + .c = &plla_characteristics, >> + }, >> + >> + { >> + .n = "plla_divpmcck", >> + .p = "plla_fracck", >> + .l = &pll_divpmc_layout, > > You mentioned in "[PATCH v4 24/39] clk: at91: sam9x7: add support for HW > PLL freq dividers" that this has div2 but it is registered w/ a layout that > has .div2 = 0. This is handled in the above plla_fracck fractional part as defined in the plla_frac_layout. > > -- Thanks and Regards, Varshini Rajendran. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel