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Tue, 8 Sep 2020 03:40:00 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Sep 2020 03:40:00 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Sep 2020 03:40:00 -0500 Received: from [192.168.2.14] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0888dvJ4022975; Tue, 8 Sep 2020 03:39:58 -0500 Subject: Re: [PATCH v2 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines To: , , References: <20200907145213.30788-1-rogerq@ti.com> <20200907145213.30788-2-rogerq@ti.com> From: Roger Quadros Message-ID: Date: Tue, 8 Sep 2020 11:39:57 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200907145213.30788-2-rogerq@ti.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_044006_674836_F1D0BF7A X-CRM114-Status: GOOD ( 18.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, nsekhar@ti.com, linux-kernel@vger.kernel.org, kishon@ti.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org +Peter On 07/09/2020 17:52, Roger Quadros wrote: > Each SERDES lane mux can select upto 4 different IPs. > There are 4 lanes in each J7200 SERDES. Define all > the possible functions in this file. > > Signed-off-by: Roger Quadros > --- > include/dt-bindings/mux/mux-j7200-wiz.h | 29 +++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 include/dt-bindings/mux/mux-j7200-wiz.h > > diff --git a/include/dt-bindings/mux/mux-j7200-wiz.h b/include/dt-bindings/mux/mux-j7200-wiz.h > new file mode 100644 > index 000000000000..b091b1185a36 > --- /dev/null > +++ b/include/dt-bindings/mux/mux-j7200-wiz.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * This header provides constants for J7200 WIZ. > + */ > + > +#ifndef _DT_BINDINGS_J7200_WIZ > +#define _DT_BINDINGS_J7200_WIZ > + > +#define SERDES0_LANE0_QSGMII_LANE3 0x0 > +#define SERDES0_LANE0_PCIE1_LANE0 0x1 > +#define SERDES0_LANE0_IP3_UNUSED 0x2 > +#define SERDES0_LANE0_IP4_UNUSED 0x3 > + > +#define SERDES0_LANE1_QSGMII_LANE4 0x0 > +#define SERDES0_LANE1_PCIE1_LANE1 0x1 > +#define SERDES0_LANE1_IP3_UNUSED 0x2 > +#define SERDES0_LANE1_IP4_UNUSED 0x3 > + > +#define SERDES0_LANE2_QSGMII_LANE1 0x0 > +#define SERDES0_LANE2_PCIE1_LANE2 0x1 > +#define SERDES0_LANE2_IP3_UNUSED 0x2 > +#define SERDES0_LANE2_IP4_UNUSED 0x3 > + > +#define SERDES0_LANE3_QSGMII_LANE2 0x0 > +#define SERDES0_LANE3_PCIE1_LANE3 0x1 > +#define SERDES0_LANE3_USB 0x2 > +#define SERDES0_LANE3_IP4_UNUSED 0x3 > + > +#endif /* _DT_BINDINGS_J7200_WIZ */ > -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. 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