From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D021FC433F5 for ; Wed, 15 Sep 2021 05:45:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7F23061131 for ; Wed, 15 Sep 2021 05:45:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7F23061131 Authentication-Results: mail.kernel.org; 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Wed, 15 Sep 2021 05:43:16 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mQNhR-00870L-6I for linux-arm-kernel@lists.infradead.org; Wed, 15 Sep 2021 05:43:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C948B31B; Tue, 14 Sep 2021 22:43:10 -0700 (PDT) Received: from [10.163.70.189] (unknown [10.163.70.189]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5EB2A3F719; Tue, 14 Sep 2021 22:43:07 -0700 (PDT) Subject: Re: [PATCH v3 06/10] coresight: trbe: Fix handling of spurious interrupts To: Suzuki K Poulose , coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, tamas.zsoldos@arm.com, jinlmao@qti.qualcomm.com, al.grant@arm.com, denik@google.com References: <20210914102641.1852544-1-suzuki.poulose@arm.com> <20210914102641.1852544-7-suzuki.poulose@arm.com> From: Anshuman Khandual Message-ID: Date: Wed, 15 Sep 2021 11:14:12 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210914102641.1852544-7-suzuki.poulose@arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210914_224313_387441_200926B5 X-CRM114-Status: GOOD ( 24.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/14/21 3:56 PM, Suzuki K Poulose wrote: > On a spurious IRQ, right now we disable the TRBE and then re-enable > it back, resetting the "buffer" pointers(i.e BASE, LIMIT and more > importantly WRITE) to the original pointers from the AUX handle. > This implies that we overwrite any trace that was written so far, > (by overwriting TRBPTR) while we should have ignored the IRQ. > > This patch cleans the behavior, by only stopping the TRBE if the > IRQ was indeed raised, as we can read the TRBSR without stopping > the TRBE (Only writes to the TRBSR requires the TRBE disabled). > And also, on detecting a spurious IRQ after examining the TRBSR, > we simply re-enable the TRBE without touching the other parameters. > > Cc: Anshuman Khandual > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Leo Yan > Signed-off-by: Suzuki K Poulose Reviewed-by: Anshuman Khandual > --- > drivers/hwtracing/coresight/coresight-trbe.c | 30 ++++++++++---------- > 1 file changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 5297b11f26b7..de99dd0aecd3 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -677,16 +677,16 @@ static int arm_trbe_disable(struct coresight_device *csdev) > > static void trbe_handle_spurious(struct perf_output_handle *handle) > { > - struct trbe_buf *buf = etm_perf_sink_config(handle); > + u64 limitr = read_sysreg_s(SYS_TRBLIMITR_EL1); > > - buf->trbe_limit = compute_trbe_buffer_limit(handle); > - buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf); > - if (buf->trbe_limit == buf->trbe_base) { > - trbe_drain_and_disable_local(); > - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); > - return; > - } > - trbe_enable_hw(buf); > + /* > + * If the IRQ was spurious, simply re-enable the TRBE > + * back without modifying the buffer parameters to > + * retain the trace collected so far. > + */ > + limitr |= TRBLIMITR_ENABLE; > + write_sysreg_s(limitr, SYS_TRBLIMITR_EL1); > + isb(); > } > > static void trbe_handle_overflow(struct perf_output_handle *handle) > @@ -759,12 +759,7 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) > enum trbe_fault_action act; > u64 status; > > - /* > - * Ensure the trace is visible to the CPUs and > - * any external aborts have been resolved. > - */ > - trbe_drain_and_disable_local(); > - > + /* Reads to TRBSR_EL1 is fine when TRBE is active */ > status = read_sysreg_s(SYS_TRBSR_EL1); > /* > * If the pending IRQ was handled by update_buffer callback > @@ -773,6 +768,11 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) > if (!is_trbe_irq(status)) > return IRQ_NONE; > > + /* > + * Ensure the trace is visible to the CPUs and > + * any external aborts have been resolved. > + */ > + trbe_drain_and_disable_local(); > clr_trbe_irq(); > isb(); > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel