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bh=4hfowH2iHudGa0LkdrtS84kdcHbiN+9po/FhXQJzKNc=; b=lDEcy0IlAKe7LED+HzIzOHqp7CRKXKALzRrQvDKmrcT+wSLI8n83tfSuSjmrDfFXpayuFZ D/To6s3CvThP/7sijhPgJ0EAXtGCAvTCiKU0hr6VoOZ2EXwEd+pirxb2DYcmsWOwxuzKe7 v2fyfqfHItH+5h09GPlqQAPfuAxAu2azo2UqNy56zXTOW4MqPFdpitQ2Xxx4iE9aNGqlC8 nb8nbZLPr4IhuTRN8T7YfzqaTccW2zL4BslS3CNut000rO3wDjAN+VZeuR/mrLzeHKRzKc ypTa4p2sU3wR40taTxUJFxAGHWs3Yr4evv0CtGzFYK5qYoB/fC8RKzR3INpzsw== Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1760482790; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4hfowH2iHudGa0LkdrtS84kdcHbiN+9po/FhXQJzKNc=; b=xUVFUheZfugfP5J1pOCixDTQUpRLR9ZwawCcYGvcbW0pX3TvbJAVoSQR0l//+64oGR/MuC blIqT6PMlEMDE32pIZjKikeZZZ6Esi+Tluf4fTwEaEqODCW8cHnbbowg5IEy5Pol3VmG/t wJdllMmbnaVfbRqAKkNHWe9SxD7JNhKUw1Iq4FYbKsa0Bd/x04aPTN5wXuX/CIicFhqQY2 NXckdpuJlHBs606HssIwzgcfZWsjPuVfR2lY02+kbvVV2raxdD0+jRTlQzkqilhKH6y4h/ TS/wUVguGXKs4890cebtTyZCBWI10ZFHQBYEgCllVDjVFIe98h00NosUuw2sug== Date: Wed, 15 Oct 2025 00:59:45 +0200 MIME-Version: 1.0 Subject: Re: [PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node To: Matt Coster , Marek Vasut Cc: Adam Ford , Conor Dooley , David Airlie , Frank Binns , Alessio Belle , Alexandru Dadu , Geert Uytterhoeven , Krzysztof Kozlowski , Kuninori Morimoto , Maarten Lankhorst , Magnus Damm , Maxime Ripard , Rob Herring , Simona Vetter , Thomas Zimmermann , "devicetree@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "linux-arm-kernel@lists.infradead.org" , "linux-renesas-soc@vger.kernel.org" References: <20251013190210.142436-1-marek.vasut+renesas@mailbox.org> <20251013190210.142436-2-marek.vasut+renesas@mailbox.org> Content-Language: en-US From: Marek Vasut In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-META: ya4auwctb7mmsqbrry9umriad1d3o4wa X-MBO-RS-ID: 34d82dfc4b4fa9568db X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251014_155954_449429_EB8D8E27 X-CRM114-Status: GOOD ( 20.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/14/25 1:52 PM, Matt Coster wrote: Hello Matt, >> +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi >> @@ -2565,6 +2565,18 @@ gic: interrupt-controller@f1010000 { >> resets = <&cpg 408>; >> }; >> >> + gpu: gpu@fd000000 { >> + compatible = "renesas,r8a77960-gpu", >> + "img,img-gx6250", >> + "img,img-rogue"; >> + reg = <0 0xfd000000 0 0x40000>; >> + interrupts = ; >> + clocks = <&cpg CPG_MOD 112>; >> + clock-names = "core"; >> + power-domains = <&sysc R8A7796_PD_3DG_B>; > > My comments here apply to the other dts patch (P3/3) as well since the > integration appears to be identical between the two SoCs. > > There are two power domains on this GPU and the SoC exposes both of > them; no reason to fall back to the single-domain scheme here. > > I know the sysc driver declares the dependency of _B on _A, but the dts > shouldn't rely on that, so can we have: > > power-domains = <&sysc R8A7796_PD_3DG_A>, <&sysc R8A7796_PD_3DG_B>; > power-domain-names = "a", "b"; Both SoCs fixed in V2 , which I will post in a few days , thanks ! >> + resets = <&cpg 112>; > > Is this a reset line? Is it a clock? This is a reset line. The MSTP controls both clocks and resets, but this particular phandle describes reset control. > I see this pattern used throughout > the Renesas dts, but I'm just thinking how this will interact with the > powervr driver. The reset line is optional since some hardware > integrations manage it for us during the power-up/down sequences, which > appears to be the case here with the MSTP control (from my brief dig > through the Renesas TRM). As far as I can tell, the pvr_power.c toggles the IP reset after the IP clock were already enabled, so the IP should be correctly reset. What kind of problem do you expect ? > Related, see my comments on the bindings patch (P1/3) about how clocks > are wired up in this SoC. I tried to reply to that one, hopefully it makes some sense.