From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01C24C7EE2E for ; Fri, 9 Jun 2023 05:23:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uZjaDeiykg81OmRaW7MGcxqosPGQ9SLh0evxha3t8Jw=; b=jLwz373ihlTRIk Fq0VuiV/mwRyastdTmHpGvwcmsLiY2KwIu6ri3LHjZgb9pF9adxKnB+/2WCvlGR3tBKac/sfAEeod E4/xiBrja+SJ3JfhjSTo516GtqkzW1Kv2F4FIlo5fsxGYFLoEG5fw7QEgDMCKkP4mYAIvWd6T+5VX 9MFaDZCdcA3/VfYogyOqmgRwisO7ilcjBz9nGzR0JJdV+rkCfenGCv8qXn7M44VkxfhshM2SjlFUs 0FNY3zHjZPIiXMdERuNtmJPvj63oghdUdaplKmneEKPUD5waNimwRO5FY6tXzfvRkFRg1WEtJuk/e l9oCdAl02JmkaZ/KmC9A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q7UaQ-00BiE3-35; Fri, 09 Jun 2023 05:22:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q7UaM-00BiCD-0P for linux-arm-kernel@lists.infradead.org; Fri, 09 Jun 2023 05:22:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DA933AB6; Thu, 8 Jun 2023 22:23:32 -0700 (PDT) Received: from [10.163.44.201] (unknown [10.163.44.201]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5262E3F587; Thu, 8 Jun 2023 22:22:41 -0700 (PDT) Message-ID: Date: Fri, 9 Jun 2023 10:52:37 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH V11 06/10] arm64/perf: Enable branch stack events via FEAT_BRBE Content-Language: en-US To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, catalin.marinas@arm.com, Mark Brown , James Clark , Rob Herring , Marc Zyngier , Suzuki Poulose , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , linux-perf-users@vger.kernel.org References: <20230531040428.501523-1-anshuman.khandual@arm.com> <20230531040428.501523-7-anshuman.khandual@arm.com> From: Anshuman Khandual In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230608_222254_287330_1CFB704C X-CRM114-Status: GOOD ( 21.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org [...] On 6/5/23 19:13, Mark Rutland wrote: >> +void armv8pmu_branch_read(struct pmu_hw_events *cpuc, struct perf_event *event) >> +{ >> + struct brbe_hw_attr *brbe_attr = (struct brbe_hw_attr *)cpuc->percpu_pmu->private; >> + u64 brbfcr, brbcr; >> + int idx, loop1_idx1, loop1_idx2, loop2_idx1, loop2_idx2, count; >> + >> + brbcr = read_sysreg_s(SYS_BRBCR_EL1); >> + brbfcr = read_sysreg_s(SYS_BRBFCR_EL1); >> + >> + /* Ensure pause on PMU interrupt is enabled */ >> + WARN_ON_ONCE(!(brbcr & BRBCR_EL1_FZP)); >> + >> + /* Pause the buffer */ >> + write_sysreg_s(brbfcr | BRBFCR_EL1_PAUSED, SYS_BRBFCR_EL1); >> + isb(); >> + >> + /* Determine the indices for each loop */ >> + loop1_idx1 = BRBE_BANK0_IDX_MIN; >> + if (brbe_attr->brbe_nr <= BRBE_BANK_MAX_ENTRIES) { >> + loop1_idx2 = brbe_attr->brbe_nr - 1; >> + loop2_idx1 = BRBE_BANK1_IDX_MIN; >> + loop2_idx2 = BRBE_BANK0_IDX_MAX; >> + } else { >> + loop1_idx2 = BRBE_BANK0_IDX_MAX; >> + loop2_idx1 = BRBE_BANK1_IDX_MIN; >> + loop2_idx2 = brbe_attr->brbe_nr - 1; >> + } >> + >> + /* Loop through bank 0 */ >> + select_brbe_bank(BRBE_BANK_IDX_0); >> + for (idx = 0, count = loop1_idx1; count <= loop1_idx2; idx++, count++) { >> + if (!capture_branch_entry(cpuc, event, idx)) >> + goto skip_bank_1; >> + } >> + >> + /* Loop through bank 1 */ >> + select_brbe_bank(BRBE_BANK_IDX_1); >> + for (count = loop2_idx1; count <= loop2_idx2; idx++, count++) { >> + if (!capture_branch_entry(cpuc, event, idx)) >> + break; >> + } >> + >> +skip_bank_1: >> + cpuc->branches->branch_stack.nr = idx; >> + cpuc->branches->branch_stack.hw_idx = -1ULL; >> + process_branch_aborts(cpuc); >> + >> + /* Unpause the buffer */ >> + write_sysreg_s(brbfcr & ~BRBFCR_EL1_PAUSED, SYS_BRBFCR_EL1); >> + isb(); >> + armv8pmu_branch_reset(); >> +} > The loop indicies are rather difficult to follow, and I think those can be made > quite a lot simpler if split out, e.g. > > | int __armv8pmu_branch_read(struct pmu_hw_events *cpuc, struct perf_event *event) > | { > | struct brbe_hw_attr *brbe_attr = (struct brbe_hw_attr *)cpuc->percpu_pmu->private; > | int nr_hw_entries = brbe_attr->brbe_nr; > | int idx; I guess idx needs an init to 0. > | > | select_brbe_bank(BRBE_BANK_IDX_0); > | while (idx < nr_hw_entries && idx < BRBE_BANK0_IDX_MAX) { > | if (!capture_branch_entry(cpuc, event, idx)) > | return idx; > | idx++; > | } > | > | select_brbe_bank(BRBE_BANK_IDX_1); > | while (idx < nr_hw_entries && idx < BRBE_BANK1_IDX_MAX) { > | if (!capture_branch_entry(cpuc, event, idx)) > | return idx; > | idx++; > | } > | > | return idx; > | } These loops are better than the proposed one with indices, will update. > | > | void armv8pmu_branch_read(struct pmu_hw_events *cpuc, struct perf_event *event) > | { > | u64 brbfcr, brbcr; > | int nr; > | > | brbcr = read_sysreg_s(SYS_BRBCR_EL1); > | brbfcr = read_sysreg_s(SYS_BRBFCR_EL1); > | > | /* Ensure pause on PMU interrupt is enabled */ > | WARN_ON_ONCE(!(brbcr & BRBCR_EL1_FZP)); > | > | /* Pause the buffer */ > | write_sysreg_s(brbfcr | BRBFCR_EL1_PAUSED, SYS_BRBFCR_EL1); > | isb(); > | > | nr = __armv8pmu_branch_read(cpus, event); > | > | cpuc->branches->branch_stack.nr = nr; > | cpuc->branches->branch_stack.hw_idx = -1ULL; > | process_branch_aborts(cpuc); > | > | /* Unpause the buffer */ > | write_sysreg_s(brbfcr & ~BRBFCR_EL1_PAUSED, SYS_BRBFCR_EL1); > | isb(); > | armv8pmu_branch_reset(); > | } > > Looking at I see: > > | /* > | * branch stack layout: > | * nr: number of taken branches stored in entries[] > | * hw_idx: The low level index of raw branch records > | * for the most recent branch. > | * -1ULL means invalid/unknown. > | * > | * Note that nr can vary from sample to sample > | * branches (to, from) are stored from most recent > | * to least recent, i.e., entries[0] contains the most > | * recent branch. > | * The entries[] is an abstraction of raw branch records, > | * which may not be stored in age order in HW, e.g. Intel LBR. > | * The hw_idx is to expose the low level index of raw > | * branch record for the most recent branch aka entries[0]. > | * The hw_idx index is between -1 (unknown) and max depth, > | * which can be retrieved in /sys/devices/cpu/caps/branches. > | * For the architectures whose raw branch records are > | * already stored in age order, the hw_idx should be 0. > | */ > | struct perf_branch_stack { > | __u64 nr; > | __u64 hw_idx; > | struct perf_branch_entry entries[]; > | }; > > ... which seems to indicate we should be setting hw_idx to 0, since IIUC our > records are in age order. Branch records are indeed in age order, sure will change hw_idx as 0. Earlier figured that there was no need for hw_idx and hence marked it as -1UL similar to other platforms like powerpc. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel