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Tue, 27 Oct 2026 02:31:53 -0700 (PDT) Received: from [0.0.0.0] ([129.126.71.118]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2eae6c9757bsm6281855ad.58.2026.10.27.02.31.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Oct 2026 02:31:52 -0700 (PDT) Message-ID: Date: Tue, 27 Oct 2026 17:31:44 +0800 X-Archived-By: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] cpufreq: add an Amlogic speed-bin driver To: Jerome Brunet , Viresh Kumar , christian.koever-draxl@student.uibk.ac.at Cc: neil.armstrong@linaro.org, sboyd@kernel.org, bmasney+clk@redhat.com, khilman@baylibre.com, martin.blumenstingl@googlemail.com, rafael@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?Q?Christian_Stefan_K=C3=B6v=C3=A9r-Draxl?= References: <20261025192219.209137-1-christian.koever-draxl@student.uibk.ac.at> <20261025192219.209137-5-christian.koever-draxl@student.uibk.ac.at> <1jbj8gkff1.fsf@starbuckisacylon.baylibre.com> From: Chuan Liu In-Reply-To: <1jbj8gkff1.fsf@starbuckisacylon.baylibre.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261027_023154_681936_0B9F3B1F X-CRM114-Status: GOOD ( 19.06 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Jerome, On 10/26/2026 4:57 PM, Jerome Brunet wrote: > On lun. 26 oct. 2026 at 11:00, Viresh Kumar wrote: > >> On 25-10-26, 20:22, christian.koever-draxl@student.uibk.ac.at wrote: >>> From: Christian Stefan Kövér-Draxl >>> >>> Every S4 speed bin runs the same CPU frequencies but needs its own >>> voltage curve, and the bin can only be read through the secure monitor. >>> >>> Read the bin from the firmware, select the matching >>> "opp-microvolt-speed" property for all CPUs, then register >>> cpufreq-dt. Bins outside the known range fall back to bin 0, which >>> has the highest voltages. Like sun50i-cpufreq-nvmem, the driver binds >>> on the SoC compatible and needs no node of its own, and S4 is added to >>> the cpufreq-dt-platdev blocklist so cpufreq-dt is only created after >>> the bin has been applied. >>> >>> Signed-off-by: Christian Stefan Kövér-Draxl >>> --- >>> MAINTAINERS | 1 + >>> drivers/cpufreq/Kconfig.arm | 14 ++ >>> drivers/cpufreq/Makefile | 1 + >>> drivers/cpufreq/amlogic-cpufreq.c | 184 +++++++++++++++++++++++++++ >>> drivers/cpufreq/cpufreq-dt-platdev.c | 2 + >>> 5 files changed, 202 insertions(+) >>> create mode 100644 drivers/cpufreq/amlogic-cpufreq.c >> >> Is it safe to apply just this one ? I can take this via the PM tree then. > > I would advise to wait a little for Amlogic to chime in.> > Patch 2 is something I already rejected back when S4 support was > initially introduced. I suppose AI just unearthed it and did not bother > to mention it. > > Amlogic was supposed to migrate to SCMI at that point, and possibly > handle CPU frequency scaling through the secure fw entirely. Yes, starting from the C3 clock upstream submission, we replaced the SMCs implementation of the secure-clock with SCMI. For the latest released Amlogic SoCs (S7 and later), secure-clock is implemented uniformly through SCMI. > > They did on later SoCs, I don't know where their FW stands on the S4. Most S4 customers receive a secure firmware (bl31.bin) that sets secure-clock via SMCs (because the S4 SDK had already been released by the time we added SCMI support). We have also provided an SCMI-capable bl31.bin to some customers. > >> >> -- >> viresh > -- Best regards, Chuan