[PATCH 0/4] mmc: sdhci-esdhc-imx: add 1-bit bus width support

[PATCH 0/4] mmc: sdhci-esdhc-imx: add 1-bit bus width support

[ziniu.wang_1]

From: Luke Wang <ziniu.wang_1@nxp.com>

This series adds 1-bit bus width support for sdhci-esdhc-imx driver.

Currently sdhci-esdhc-imx doesn't support 1-bit width because it
doesn't call sdhci_get_property() to parse "bus-width = <1>" and
set SDHCI_QUIRK_FORCE_1_BIT_DATA quirk.

After adding sdhci_get_property(), another issue is exposed:
mmc_select_hs200() returns 0 without switching when 1-bit bus is
used, causing mmc_select_timing() to skip mmc_select_hs(). This
leaves eMMC in legacy mode (26MHz) instead of High Speed (52MHz).

Fix by dropping incompatible UHS/DDR/HS200/HS400 caps in
mmc_validate_host_caps() for 1-bit width, and clean up duplicate
code now handled by common framework.

Luke Wang (4):
  mmc: core: fix timing selection for 1-bit bus width
  mmc: sdhci-esdhc-imx: add 1-bit bus width support
  mmc: sdhci-esdhc-imx: remove duplicate HS400 bus width validation
  mmc: sdhci-pltfm: remove duplicate DTS property parsing

 drivers/mmc/core/host.c            | 19 ++++++++++++++-----
 drivers/mmc/host/sdhci-esdhc-imx.c |  6 +-----
 drivers/mmc/host/sdhci-pltfm.c     |  7 -------
 3 files changed, 15 insertions(+), 17 deletions(-)

-- 
2.34.1

[PATCH 1/4] mmc: core: fix timing selection for 1-bit bus width

[ziniu.wang_1]

From: Luke Wang <ziniu.wang_1@nxp.com>

When 1-bit bus width is used with HS200/HS400 capabilities set,
mmc_select_hs200() returns 0 without actually switching. This
causes mmc_select_timing() to skip mmc_select_hs(), leaving eMMC
in legacy mode (26MHz) instead of High Speed SDR (52MHz).

Per JEDEC eMMC spec section 5.3.2, 1-bit width supports High Speed
SDR. Drop incompatible HS200/HS400/UHS/DDR caps early so timing
selection falls through to mmc_select_hs() correctly.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
---
 drivers/mmc/core/host.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 88c95dbfd9cf..18b9c3174e1f 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -617,17 +617,26 @@ EXPORT_SYMBOL(devm_mmc_alloc_host);
 static int mmc_validate_host_caps(struct mmc_host *host)
 {
 	struct device *dev = host->parent;
-	u32 caps = host->caps, caps2 = host->caps2;
 
-	if (caps & MMC_CAP_SDIO_IRQ && !host->ops->enable_sdio_irq) {
+	if (host->caps & MMC_CAP_SDIO_IRQ && !host->ops->enable_sdio_irq) {
 		dev_warn(dev, "missing ->enable_sdio_irq() ops\n");
 		return -EINVAL;
 	}
 
-	if (caps2 & (MMC_CAP2_HS400_ES | MMC_CAP2_HS400) &&
-	    !(caps & MMC_CAP_8_BIT_DATA) && !(caps2 & MMC_CAP2_NO_MMC)) {
+	/* UHS/DDR/HS200/HS400 modes require at least 4-bit bus */
+	if (!(host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) &&
+	    ((host->caps & (MMC_CAP_UHS | MMC_CAP_DDR)) ||
+	     (host->caps2 & (MMC_CAP2_HS200 | MMC_CAP2_HS400_ES | MMC_CAP2_HS400)))) {
+		dev_warn(dev, "drop UHS/DDR/HS200/HS400 support since 1-bit bus only\n");
+		host->caps &= ~(MMC_CAP_UHS | MMC_CAP_DDR);
+		host->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400_ES | MMC_CAP2_HS400);
+	}
+
+	if (host->caps2 & (MMC_CAP2_HS400_ES | MMC_CAP2_HS400) &&
+	    !(host->caps & MMC_CAP_8_BIT_DATA) &&
+	    !(host->caps2 & MMC_CAP2_NO_MMC)) {
 		dev_warn(dev, "drop HS400 support since no 8-bit bus\n");
-		host->caps2 = caps2 & ~MMC_CAP2_HS400_ES & ~MMC_CAP2_HS400;
+		host->caps2 &= ~(MMC_CAP2_HS400_ES | MMC_CAP2_HS400);
 	}
 
 	return 0;
-- 
2.34.1

[PATCH 2/4] mmc: sdhci-esdhc-imx: add 1-bit bus width support

[ziniu.wang_1]

From: Luke Wang <ziniu.wang_1@nxp.com>

Add sdhci_get_property() call to parse common SDHCI DT properties,
including "bus-width = <1>" which sets SDHCI_QUIRK_FORCE_1_BIT_DATA
quirk for 1-bit data bus width configuration.

Remove the duplicate "no-1-8-v" property parsing since
sdhci_get_property() already handles it.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 97461e20425d..b607d4ffc562 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1813,8 +1813,6 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 
 	of_property_read_u32(np, "fsl,strobe-dll-delay-target",
 				&boarddata->strobe_dll_delay_target);
-	if (of_property_read_bool(np, "no-1-8-v"))
-		host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
 
 	if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
 		boarddata->delay_line = 0;
@@ -1833,6 +1831,8 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 	if (ret)
 		return ret;
 
+	sdhci_get_property(pdev);
+
 	/* HS400/HS400ES require 8 bit bus */
 	if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA))
 		host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
-- 
2.34.1

[PATCH 3/4] mmc: sdhci-esdhc-imx: remove duplicate HS400 bus width validation

[ziniu.wang_1]

From: Luke Wang <ziniu.wang_1@nxp.com>

mmc_validate_host_caps() already validates that HS400/HS400ES requires
8-bit bus width. Remove the duplicate validation.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index b607d4ffc562..d49069986efc 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1833,10 +1833,6 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 
 	sdhci_get_property(pdev);
 
-	/* HS400/HS400ES require 8 bit bus */
-	if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA))
-		host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
-
 	if (mmc_gpio_get_cd(host->mmc) >= 0)
 		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 
-- 
2.34.1

[PATCH 4/4] mmc: sdhci-pltfm: remove duplicate DTS property parsing

[ziniu.wang_1]

From: Luke Wang <ziniu.wang_1@nxp.com>

The "keep-power-in-suspend", "wakeup-source" and "enable-sdio-wakeup"
properties are already parsed in mmc_of_parse(). All sdhci drivers that
call sdhci_get_property() also call mmc_of_parse(). The only exception
is sdhci-of-hlwd, which does not call mmc_of_parse(), but its devicetree
does not use these properties anyway.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
---
 drivers/mmc/host/sdhci-pltfm.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index d4fb60c1ef69..933fafe0a0ef 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -95,13 +95,6 @@ void sdhci_get_property(struct platform_device *pdev)
 	sdhci_get_compatibility(pdev);
 
 	device_property_read_u32(dev, "clock-frequency", &pltfm_host->clock);
-
-	if (device_property_present(dev, "keep-power-in-suspend"))
-		host->mmc->pm_caps |= MMC_PM_KEEP_POWER;
-
-	if (device_property_read_bool(dev, "wakeup-source") ||
-	    device_property_read_bool(dev, "enable-sdio-wakeup")) /* legacy */
-		host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
 }
 EXPORT_SYMBOL_GPL(sdhci_get_property);
 
-- 
2.34.1

Re: [PATCH 1/4] mmc: core: fix timing selection for 1-bit bus width

[Shawn Lin]

Hi Luke

在 2026/03/02 星期一 16:00, ziniu.wang_1@nxp.com 写道:
> From: Luke Wang <ziniu.wang_1@nxp.com>
> 
> When 1-bit bus width is used with HS200/HS400 capabilities set,
> mmc_select_hs200() returns 0 without actually switching. This
> causes mmc_select_timing() to skip mmc_select_hs(), leaving eMMC
> in legacy mode (26MHz) instead of High Speed SDR (52MHz).
> 
> Per JEDEC eMMC spec section 5.3.2, 1-bit width supports High Speed
> SDR. Drop incompatible HS200/HS400/UHS/DDR caps early so timing
> selection falls through to mmc_select_hs() correctly.
> 

I've tested this patch, and it works as intended.

Unrelated to your specific change, however, I'm not convinced that
mmc_validate_host_caps() is doing what its name suggests, at least not
comprehensively. For example, the SD card path handles 1-bit bus with
UHS support correctly, thanks to the mmc_host_uhs() check inside the
SD/SDIO code. This makes the validation logic feel scattered across
different layers IMO. It would be even better if you could consolidate 
all these checks in one place maybe, but anyway

Tested-by: Shawn Lin <shawn.lin@rock-chips.com>


> Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
> ---
>   drivers/mmc/core/host.c | 19 ++++++++++++++-----
>   1 file changed, 14 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
> index 88c95dbfd9cf..18b9c3174e1f 100644
> --- a/drivers/mmc/core/host.c
> +++ b/drivers/mmc/core/host.c
> @@ -617,17 +617,26 @@ EXPORT_SYMBOL(devm_mmc_alloc_host);
>   static int mmc_validate_host_caps(struct mmc_host *host)
>   {
>   	struct device *dev = host->parent;
> -	u32 caps = host->caps, caps2 = host->caps2;
>   
> -	if (caps & MMC_CAP_SDIO_IRQ && !host->ops->enable_sdio_irq) {
> +	if (host->caps & MMC_CAP_SDIO_IRQ && !host->ops->enable_sdio_irq) {
>   		dev_warn(dev, "missing ->enable_sdio_irq() ops\n");
>   		return -EINVAL;
>   	}
>   
> -	if (caps2 & (MMC_CAP2_HS400_ES | MMC_CAP2_HS400) &&
> -	    !(caps & MMC_CAP_8_BIT_DATA) && !(caps2 & MMC_CAP2_NO_MMC)) {
> +	/* UHS/DDR/HS200/HS400 modes require at least 4-bit bus */
> +	if (!(host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) &&
> +	    ((host->caps & (MMC_CAP_UHS | MMC_CAP_DDR)) ||
> +	     (host->caps2 & (MMC_CAP2_HS200 | MMC_CAP2_HS400_ES | MMC_CAP2_HS400)))) {
> +		dev_warn(dev, "drop UHS/DDR/HS200/HS400 support since 1-bit bus only\n");
> +		host->caps &= ~(MMC_CAP_UHS | MMC_CAP_DDR);
> +		host->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400_ES | MMC_CAP2_HS400);
> +	}
> +
> +	if (host->caps2 & (MMC_CAP2_HS400_ES | MMC_CAP2_HS400) &&
> +	    !(host->caps & MMC_CAP_8_BIT_DATA) &&
> +	    !(host->caps2 & MMC_CAP2_NO_MMC)) {
>   		dev_warn(dev, "drop HS400 support since no 8-bit bus\n");
> -		host->caps2 = caps2 & ~MMC_CAP2_HS400_ES & ~MMC_CAP2_HS400;
> +		host->caps2 &= ~(MMC_CAP2_HS400_ES | MMC_CAP2_HS400);
>   	}
>   
>   	return 0;
> 

Re: [PATCH 0/4] mmc: sdhci-esdhc-imx: add 1-bit bus width support

[Adrian Hunter]

On 02/03/2026 10:00, ziniu.wang_1@nxp.com wrote:
> From: Luke Wang <ziniu.wang_1@nxp.com>
> 
> This series adds 1-bit bus width support for sdhci-esdhc-imx driver.
> 
> Currently sdhci-esdhc-imx doesn't support 1-bit width because it
> doesn't call sdhci_get_property() to parse "bus-width = <1>" and
> set SDHCI_QUIRK_FORCE_1_BIT_DATA quirk.
> 
> After adding sdhci_get_property(), another issue is exposed:
> mmc_select_hs200() returns 0 without switching when 1-bit bus is
> used, causing mmc_select_timing() to skip mmc_select_hs(). This
> leaves eMMC in legacy mode (26MHz) instead of High Speed (52MHz).

How do you end up with incompatible caps?  If sdhci is adding
them, then maybe stop that instead of removing them later?

> 
> Fix by dropping incompatible UHS/DDR/HS200/HS400 caps in
> mmc_validate_host_caps() for 1-bit width, and clean up duplicate
> code now handled by common framework.
> 
> Luke Wang (4):
>   mmc: core: fix timing selection for 1-bit bus width
>   mmc: sdhci-esdhc-imx: add 1-bit bus width support
>   mmc: sdhci-esdhc-imx: remove duplicate HS400 bus width validation
>   mmc: sdhci-pltfm: remove duplicate DTS property parsing
> 
>  drivers/mmc/core/host.c            | 19 ++++++++++++++-----
>  drivers/mmc/host/sdhci-esdhc-imx.c |  6 +-----
>  drivers/mmc/host/sdhci-pltfm.c     |  7 -------
>  3 files changed, 15 insertions(+), 17 deletions(-)
> 

RE: [EXT] Re: [PATCH 0/4] mmc: sdhci-esdhc-imx: add 1-bit bus width support

[Luke Wang]

> -----Original Message-----
> From: Adrian Hunter <adrian.hunter@intel.com>
> Sent: Monday, March 2, 2026 9:45 PM
> To: Luke Wang <ziniu.wang_1@nxp.com>; ulf.hansson@linaro.org; Bough
> Chen <haibo.chen@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; imx@lists.linux.dev; linux-
> mmc@vger.kernel.org; dl-S32 <S32@nxp.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [PATCH 0/4] mmc: sdhci-esdhc-imx: add 1-bit bus width
> support
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
> 
> 
> On 02/03/2026 10:00, ziniu.wang_1@nxp.com wrote:
> > From: Luke Wang <ziniu.wang_1@nxp.com>
> >
> > This series adds 1-bit bus width support for sdhci-esdhc-imx driver.
> >
> > Currently sdhci-esdhc-imx doesn't support 1-bit width because it
> > doesn't call sdhci_get_property() to parse "bus-width = <1>" and
> > set SDHCI_QUIRK_FORCE_1_BIT_DATA quirk.
> >
> > After adding sdhci_get_property(), another issue is exposed:
> > mmc_select_hs200() returns 0 without switching when 1-bit bus is
> > used, causing mmc_select_timing() to skip mmc_select_hs(). This
> > leaves eMMC in legacy mode (26MHz) instead of High Speed (52MHz).
> 
> How do you end up with incompatible caps?  If sdhci is adding
> them, then maybe stop that instead of removing them later?

The incompatible caps come from sdhci_setup_host() in sdhci.c, where
UHS/DDR/HS200/HS400 caps are added based on hardware capability registers
without checking bus width.

I can add bus width check directly in the condition, like:

    /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
+   /* UHS modes require at least 4-bit bus width */
-   if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
-                      SDHCI_SUPPORT_DDR50))
+   if ((mmc->caps & MMC_CAP_4_BIT_DATA) &&
+       (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+                       SDHCI_SUPPORT_DDR50)))
        mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;

Similar changes for SDR104/HS200/DDR50/HS400 settings.

Is this the right approach?

Thanks,
Luke

> 
> >
> > Fix by dropping incompatible UHS/DDR/HS200/HS400 caps in
> > mmc_validate_host_caps() for 1-bit width, and clean up duplicate
> > code now handled by common framework.
> >
> > Luke Wang (4):
> >   mmc: core: fix timing selection for 1-bit bus width
> >   mmc: sdhci-esdhc-imx: add 1-bit bus width support
> >   mmc: sdhci-esdhc-imx: remove duplicate HS400 bus width validation
> >   mmc: sdhci-pltfm: remove duplicate DTS property parsing
> >
> >  drivers/mmc/core/host.c            | 19 ++++++++++++++-----
> >  drivers/mmc/host/sdhci-esdhc-imx.c |  6 +-----
> >  drivers/mmc/host/sdhci-pltfm.c     |  7 -------
> >  3 files changed, 15 insertions(+), 17 deletions(-)
> >

Re: [EXT] Re: [PATCH 0/4] mmc: sdhci-esdhc-imx: add 1-bit bus width support

[Adrian Hunter]

On 03/03/2026 05:39, Luke Wang wrote:
> 
> 
>> -----Original Message-----
>> From: Adrian Hunter <adrian.hunter@intel.com>
>> Sent: Monday, March 2, 2026 9:45 PM
>> To: Luke Wang <ziniu.wang_1@nxp.com>; ulf.hansson@linaro.org; Bough
>> Chen <haibo.chen@nxp.com>
>> Cc: Frank Li <frank.li@nxp.com>; s.hauer@pengutronix.de;
>> kernel@pengutronix.de; festevam@gmail.com; imx@lists.linux.dev; linux-
>> mmc@vger.kernel.org; dl-S32 <S32@nxp.com>; linux-arm-
>> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
>> Subject: [EXT] Re: [PATCH 0/4] mmc: sdhci-esdhc-imx: add 1-bit bus width
>> support
>>
>> Caution: This is an external email. Please take care when clicking links or
>> opening attachments. When in doubt, report the message using the 'Report
>> this email' button
>>
>>
>> On 02/03/2026 10:00, ziniu.wang_1@nxp.com wrote:
>>> From: Luke Wang <ziniu.wang_1@nxp.com>
>>>
>>> This series adds 1-bit bus width support for sdhci-esdhc-imx driver.
>>>
>>> Currently sdhci-esdhc-imx doesn't support 1-bit width because it
>>> doesn't call sdhci_get_property() to parse "bus-width = <1>" and
>>> set SDHCI_QUIRK_FORCE_1_BIT_DATA quirk.
>>>
>>> After adding sdhci_get_property(), another issue is exposed:
>>> mmc_select_hs200() returns 0 without switching when 1-bit bus is
>>> used, causing mmc_select_timing() to skip mmc_select_hs(). This
>>> leaves eMMC in legacy mode (26MHz) instead of High Speed (52MHz).
>>
>> How do you end up with incompatible caps?  If sdhci is adding
>> them, then maybe stop that instead of removing them later?
> 
> The incompatible caps come from sdhci_setup_host() in sdhci.c, where
> UHS/DDR/HS200/HS400 caps are added based on hardware capability registers
> without checking bus width.
> 
> I can add bus width check directly in the condition, like:
> 
>     /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
> +   /* UHS modes require at least 4-bit bus width */
> -   if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
> -                      SDHCI_SUPPORT_DDR50))
> +   if ((mmc->caps & MMC_CAP_4_BIT_DATA) &&
> +       (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
> +                       SDHCI_SUPPORT_DDR50)))
>         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
> 
> Similar changes for SDR104/HS200/DDR50/HS400 settings.
> 
> Is this the right approach?

I think SDHCI_QUIRK_FORCE_1_BIT_DATA should override the hardware
capabilities, similar to SDHCI_QUIRK2_NO_1_8_V.  So something like:

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index b1a3cd574c84..605be55f8d2d 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -4539,8 +4539,15 @@ int sdhci_setup_host(struct sdhci_host *host)
 	 * their platform code before calling sdhci_add_host(), and we
 	 * won't assume 8-bit width for hosts without that CAP.
 	 */
-	if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
+	if (host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA) {
+		host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+		if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400)
+			host->caps1 &= ~SDHCI_SUPPORT_HS400;
+		mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
+		mmc->caps &= ~(MMC_CAP_DDR | MMC_CAP_UHS);
+	} else {
 		mmc->caps |= MMC_CAP_4_BIT_DATA;
+	}
 
 	if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
 		mmc->caps &= ~MMC_CAP_CMD23;


> 
> Thanks,
> Luke
> 
>>
>>>
>>> Fix by dropping incompatible UHS/DDR/HS200/HS400 caps in
>>> mmc_validate_host_caps() for 1-bit width, and clean up duplicate
>>> code now handled by common framework.
>>>
>>> Luke Wang (4):
>>>   mmc: core: fix timing selection for 1-bit bus width
>>>   mmc: sdhci-esdhc-imx: add 1-bit bus width support
>>>   mmc: sdhci-esdhc-imx: remove duplicate HS400 bus width validation
>>>   mmc: sdhci-pltfm: remove duplicate DTS property parsing
>>>
>>>  drivers/mmc/core/host.c            | 19 ++++++++++++++-----
>>>  drivers/mmc/host/sdhci-esdhc-imx.c |  6 +-----
>>>  drivers/mmc/host/sdhci-pltfm.c     |  7 -------
>>>  3 files changed, 15 insertions(+), 17 deletions(-)
>>>
>