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dkim=none (message not signed) header.d=none;dmarc=fail action=none header.from=foss.st.com; Received-SPF: Fail (protection.outlook.com: domain of foss.st.com does not designate 164.130.1.87 as permitted sender) receiver=protection.outlook.com; client-ip=164.130.1.87; helo=smtpO365.st.com; Received: from smtpO365.st.com (164.130.1.87) by DB1PEPF000509EB.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.3 via Frontend Transport; Mon, 31 Aug 2026 14:01:26 +0000 Received: from ENXDAG1NODE4.st.com (10.75.129.197) by smtpo365.st.com (10.250.44.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Mon, 31 Aug 2026 16:03:24 +0200 Received: from [10.48.87.20] (10.48.87.20) by ENXDAG1NODE4.st.com (10.75.129.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Mon, 31 Aug 2026 16:01:24 +0200 Message-ID: Date: Mon, 31 Aug 2026 16:01:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/9] dmaengine: stm32-dma3: Use bus width capability helpers To: =?UTF-8?Q?Nuno_S=C3=A1?= , , , , , , , , CC: Vinod Koul , Frank Li , "Lars-Peter Clausen" , Eugeniy Paltsev , Maxime Coquelin , Alexandre Torgue , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Jaroslav Kysela" , Takashi Iwai , Mark Brown , Frank Li References: <20260831-dmaengine-support-wider-dma-masks-v3-0-507d97496f2d@analog.com> <20260831-dmaengine-support-wider-dma-masks-v3-5-507d97496f2d@analog.com> Content-Language: en-US From: Amelie Delaunay In-Reply-To: <20260831-dmaengine-support-wider-dma-masks-v3-5-507d97496f2d@analog.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lQ5J6/XuSl7bmwg0CHTWGaAPqk1Ep5MrJV83Qsav5vUkYbJtdaNgX8BxntTyF56qX66/6CT5vY1IZtHQ7OPQTT0w05dndPXd6AfNlWHQNWcRjc2BDb0ruFPHJOREIhDlHK0dqPGbNGhuUrEU9fNfEcw0tlD5WCFINXLu77x8Zl2CY0rGciNMilxv3tO4z0FOVvl1EkuLhnfB0hxflEhyvX1AhsoehU7r3bTyzWITfNlFVn6GCQenJD+2HKodzShO2nbJstIxHJcdgCeLr3O3so6aCrzinDxJk9MrDuUBp14ssuKfDwEXGLEXtCg8oJRL2TgwrlqMoR8n0lI4eGAVYNJBwB/8AlIXXxxrEPeZA4U6gfErrH2nruqsAglOaM0mIZ9aXFs05XuRRQKyaJigu59N6swGhJNCXX+vLyVx6PSg1AYWWyzUy2TojL+nQv0a X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2026 14:01:26.5344 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb58c925-3e9f-4bab-47dd-08df07685954 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.87];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EB.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR10MB8762 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_070140_000666_8084EA2F X-CRM114-Status: GOOD ( 22.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Thanks for the updates! On 8/31/26 13:46, Nuno Sá wrote: > Advertise the controller-wide bus width capabilities through the new > dma_bus_width_set_many() helper and clear the per-channel unsupported > widths through dma_bus_width_clear(). > > While at it, validate the requested transfer bus widths against the new > capability mask instead of the legacy u32 one. Besides not depending on > the legacy field anymore, this also stops BIT() from being fed a bus > width coming from the device tree without any bound check. > > Reviewed-by: Frank Li > Signed-off-by: Nuno Sá > --- > drivers/dma/stm32/stm32-dma3.c | 34 +++++++++++++++++++++------------- > 1 file changed, 21 insertions(+), 13 deletions(-) > > diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c > index 4724e7fa0008..0689aeb7cff5 100644 > --- a/drivers/dma/stm32/stm32-dma3.c > +++ b/drivers/dma/stm32/stm32-dma3.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -588,7 +589,8 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf > dbl_max = chan->dma_config.dst_maxburst ? : 1; > > /* Following conditions would raise User Setting Error interrupt */ > - if (!(dma_device.src_addr_widths & BIT(sdw)) || !(dma_device.dst_addr_widths & BIT(ddw))) { > + if (!dma_bus_width_test(dma_device.src_bus_widths, sdw) || > + !dma_bus_width_test(dma_device.dst_bus_widths, ddw)) { Just to come back to one point you mentioned in your cover letter, "this stops BIT() from being fed an unvalidated device tree bus width". Here, sdw and ddw are set either by dma_config.[src|dst]_addr_width, or forced to DMA_SLAVE_BUSWIDTH_4_BYTES or DMA_SLAVE_BUSWIDTH_8_BYTES depending on the channel capabilities. So, unless I'm missing something, they do not come from an "unvalidated *device tree* bus width". Anyway, it's great to see another use of the new API. > dev_err(chan2dev(chan), "Bus width (src=%u, dst=%u) not supported\n", sdw, ddw); > return -EINVAL; > } > @@ -1469,14 +1471,14 @@ static void stm32_dma3_caps(struct dma_chan *c, struct dma_slave_caps *caps) > > if (!chan->fifo_size) { > caps->max_burst = 0; > - caps->src_addr_widths &= ~BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); > - caps->dst_addr_widths &= ~BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); > + dma_bus_width_clear(caps->src_bus_widths, DMA_SLAVE_BUSWIDTH_8_BYTES); > + dma_bus_width_clear(caps->dst_bus_widths, DMA_SLAVE_BUSWIDTH_8_BYTES); > } else { > /* Burst transfer should not exceed half of the fifo size */ > caps->max_burst = chan->max_burst; > if (caps->max_burst < DMA_SLAVE_BUSWIDTH_8_BYTES) { > - caps->src_addr_widths &= ~BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); > - caps->dst_addr_widths &= ~BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); > + dma_bus_width_clear(caps->src_bus_widths, DMA_SLAVE_BUSWIDTH_8_BYTES); > + dma_bus_width_clear(caps->dst_bus_widths, DMA_SLAVE_BUSWIDTH_8_BYTES); > } > } > } > @@ -1734,6 +1736,12 @@ static int stm32_dma3_probe(struct platform_device *pdev) > struct reset_control *reset; > struct stm32_dma3_chan *chan; > struct dma_device *dma_dev; > + enum dma_slave_buswidth buswidths[] = { > + DMA_SLAVE_BUSWIDTH_1_BYTE, > + DMA_SLAVE_BUSWIDTH_2_BYTES, > + DMA_SLAVE_BUSWIDTH_4_BYTES, > + DMA_SLAVE_BUSWIDTH_8_BYTES, > + }; > u32 master_ports, chan_reserved, i, verr; > u64 hwcfgr; > int ret; > @@ -1775,14 +1783,14 @@ static int stm32_dma3_probe(struct platform_device *pdev) > * channel, and can only access address at even boundaries, multiple of the buswidth. > */ > dma_dev->copy_align = DMAENGINE_ALIGN_8_BYTES; > - dma_dev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | > - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | > - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | > - BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); > - dma_dev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | > - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | > - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | > - BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); > + ret = dma_bus_width_set_many(dma_dev->src_bus_widths, buswidths, ARRAY_SIZE(buswidths)); > + if (ret) > + goto err_clk_disable; > + > + ret = dma_bus_width_set_many(dma_dev->dst_bus_widths, buswidths, ARRAY_SIZE(buswidths)); > + if (ret) > + goto err_clk_disable; > + > dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | BIT(DMA_MEM_TO_MEM); > > dma_dev->descriptor_reuse = true; > It looks nicer this way. Thanks! Reviewed-by: Amelie Delaunay Regards, Amelie