From: John Garry <john.garry@huawei.com>
To: Robin Murphy <robin.murphy@arm.com>, Will Deacon <will@kernel.org>
Cc: "trivial@kernel.org" <trivial@kernel.org>,
"maz@kernel.org" <maz@kernel.org>,
"joro@8bytes.org" <joro@8bytes.org>,
Linuxarm <linuxarm@huawei.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 0/4] iommu/arm-smmu-v3: Improve cmdq lock efficiency
Date: Thu, 16 Jul 2020 12:30:30 +0100 [thread overview]
Message-ID: <eba2b8f4-2e3c-5e1d-b0b3-0d76a10c64fa@huawei.com> (raw)
In-Reply-To: <aef1e4a4-d594-f477-9029-8f4295bb9f6c@arm.com>
On 16/07/2020 12:22, Robin Murphy wrote:
> On 2020-07-16 11:56, John Garry wrote:
>> On 16/07/2020 11:28, Will Deacon wrote:
>>> On Thu, Jul 16, 2020 at 11:22:33AM +0100, Will Deacon wrote:
>>>> On Thu, Jul 16, 2020 at 11:19:41AM +0100, Will Deacon wrote:
>>>>> On Tue, Jun 23, 2020 at 01:28:36AM +0800, John Garry wrote:
>>>>>> As mentioned in [0], the CPU may consume many cycles processing
>>>>>> arm_smmu_cmdq_issue_cmdlist(). One issue we find is the cmpxchg()
>>>>>> loop to
>>>>>> get space on the queue takes approx 25% of the cycles for this
>>>>>> function.
>>>>>>
>>>>>> This series removes that cmpxchg().
>>>>>
>>>>> How about something much simpler like the diff below? >>
>>>> Ah, scratch that, I don't drop the lock if we fail the cas with it held.
>>>> Let me hack it some more (I have no hardware so I can only build-test
>>>> this).
>>>
>>> Right, second attempt...
>>
>> I can try it, but if performance if not as good, then please check mine
>> further (patch 4/4 specifically) - performance is really good, IMHO.
>
> Perhaps a silly question (I'm too engrossed in PMU world ATM to get
> properly back up to speed on this), but couldn't this be done without
> cmpxchg anyway? Instinctively it feels like instead of maintaining a
> literal software copy of the prod value, we could resolve the "claim my
> slot in the queue" part with atomic_fetch_add on a free-running 32-bit
> "pseudo-prod" index, then whoever updates the hardware deals with the
> truncation and wrap bit to convert it to an actual register value.
>
That's what mine does. But I also need to take care of cmdq locking and
how we unconditionally provide space.
Cheers,
John
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next prev parent reply other threads:[~2020-07-16 11:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1592846920-45338-1-git-send-email-john.garry@huawei.com>
2020-07-08 13:00 ` [PATCH 0/4] iommu/arm-smmu-v3: Improve cmdq lock efficiency John Garry
2020-07-16 10:19 ` Will Deacon
2020-07-16 10:22 ` Will Deacon
2020-07-16 10:28 ` Will Deacon
2020-07-16 10:56 ` John Garry
2020-07-16 11:22 ` Robin Murphy
2020-07-16 11:30 ` John Garry [this message]
2020-07-16 11:32 ` Will Deacon
2020-07-16 16:50 ` John Garry
2020-07-16 13:31 ` John Garry
[not found] ` <1592846920-45338-5-git-send-email-john.garry@huawei.com>
[not found] ` <202006230905.3HpPgtSC%lkp@intel.com>
[not found] ` <5ba2e240-b324-d316-c00c-38c03ee49baa@huawei.com>
2020-06-23 16:22 ` [PATCH 4/4] iommu/arm-smmu-v3: Remove cmpxchg() in arm_smmu_cmdq_issue_cmdlist() Robin Murphy
2020-06-24 8:15 ` John Garry
[not found] ` <CADRDgG4=uD3Ni6r7D3kHdSo=ketaXKGririHfFvPYq4qz8KjfQ@mail.gmail.com>
[not found] ` <ee2d7a1e-3e22-f25a-ced9-82ccced28f8c@huawei.com>
[not found] ` <CADRDgG5pOstGK=fm8s3Be_v8+vc-EyRYmpiMsTCeK-rMk2ZRQQ@mail.gmail.com>
2020-06-26 10:05 ` John Garry
2020-07-16 10:20 ` Will Deacon
2020-07-16 10:26 ` John Garry
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