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Tue, 31 Aug 2021 15:39:16 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4AFA510002A; Tue, 31 Aug 2021 15:39:13 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 22513246929; Tue, 31 Aug 2021 15:39:13 +0200 (CEST) Received: from [10.211.11.146] (10.75.127.46) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 31 Aug 2021 15:39:11 +0200 Subject: Re: [PATCH v16 01/14] counter: stm32-lptimer-cnt: Provide defines for clock polarities To: William Breathitt Gray , CC: , , , , , , , , , , , , , , , , References: From: Fabrice Gasnier Message-ID: Date: Tue, 31 Aug 2021 15:38:50 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-08-31_05,2021-08-31_01,2020-04-07_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210831_064022_051909_730A2B0D X-CRM114-Status: GOOD ( 20.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/27/21 5:47 AM, William Breathitt Gray wrote: > The STM32 low-power timer permits configuration of the clock polarity > via the LPTIMX_CFGR register CKPOL bits. This patch provides > preprocessor defines for the supported clock polarities. > > Cc: Fabrice Gasnier > Signed-off-by: William Breathitt Gray > --- > drivers/counter/stm32-lptimer-cnt.c | 6 +++--- > include/linux/mfd/stm32-lptimer.h | 5 +++++ > 2 files changed, 8 insertions(+), 3 deletions(-) Hi William, You can add my: Reviewed-by: Fabrice Gasnier Thanks, Fabrice > > diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c > index 13656957c45f..7367f46c6f91 100644 > --- a/drivers/counter/stm32-lptimer-cnt.c > +++ b/drivers/counter/stm32-lptimer-cnt.c > @@ -140,9 +140,9 @@ static const enum counter_function stm32_lptim_cnt_functions[] = { > }; > > enum stm32_lptim_synapse_action { > - STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE, > - STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE, > - STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES, > + STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE = STM32_LPTIM_CKPOL_RISING_EDGE, > + STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE = STM32_LPTIM_CKPOL_FALLING_EDGE, > + STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES = STM32_LPTIM_CKPOL_BOTH_EDGES, > STM32_LPTIM_SYNAPSE_ACTION_NONE, > }; > > diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h > index 90b20550c1c8..06d3f11dc3c9 100644 > --- a/include/linux/mfd/stm32-lptimer.h > +++ b/include/linux/mfd/stm32-lptimer.h > @@ -45,6 +45,11 @@ > #define STM32_LPTIM_PRESC GENMASK(11, 9) > #define STM32_LPTIM_CKPOL GENMASK(2, 1) > > +/* STM32_LPTIM_CKPOL */ > +#define STM32_LPTIM_CKPOL_RISING_EDGE 0 > +#define STM32_LPTIM_CKPOL_FALLING_EDGE 1 > +#define STM32_LPTIM_CKPOL_BOTH_EDGES 2 > + > /* STM32_LPTIM_ARR */ > #define STM32_LPTIM_MAX_ARR 0xFFFF > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel