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24 Mar 2021 14:03:47 +0000 Received: from EX13MTAUWB001.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan2.pdx.amazon.com [10.236.137.194]) by email-inbound-relay-2b-c300ac87.us-west-2.amazon.com (Postfix) with ESMTPS id 6F6C0A2626; Wed, 24 Mar 2021 14:03:46 +0000 (UTC) Received: from EX13D21UWB001.ant.amazon.com (10.43.161.108) by EX13MTAUWB001.ant.amazon.com (10.43.161.249) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 24 Mar 2021 14:03:46 +0000 Received: from EX13MTAUWA001.ant.amazon.com (10.43.160.58) by EX13D21UWB001.ant.amazon.com (10.43.161.108) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 24 Mar 2021 14:03:46 +0000 Received: from [192.168.12.56] (10.1.212.27) by mail-relay.amazon.com (10.43.160.118) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 24 Mar 2021 14:03:42 +0000 Subject: Re: [PATCH v4 0/3] Fix pinctrl-single pcs_pin_dbg_show() To: Drew Fustini CC: , , , , , , , , , , , , , , References: <20210319152133.28705-1-hhhawa@amazon.com> <20210322055631.GB392062@x1> From: "Hawa, Hanna" Message-ID: Date: Wed, 24 Mar 2021 16:03:41 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210322055631.GB392062@x1> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210324_140358_550155_83756FDB X-CRM114-Status: GOOD ( 16.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 3/22/2021 7:56 AM, Drew Fustini wrote: > I'm curious what SoC are you using? I'm working on Amazon Annapurna Labs SoCs (based on ARM cortex processors). That include multiple pins controlled with same register. > > It's good to know who has hardware to test bits_per_mux in the future. > > I pay attention to pinctrl-single as that is the driver used for the TI > AM3358 SoC used in a variety of BeagleBone boards. It does not use > bits_per_mux, but I can verify that this does not cause any regression > for the AM3358 SoC: > > /sys/kernel/debug/pinctrl/44e10800.pinmux-pinctrl-single# cat pins > registered pins: 142 > pin 0 (PIN0) 0:? 44e10800 00000027 pinctrl-single > pin 1 (PIN1) 0:? 44e10804 00000027 pinctrl-single > pin 2 (PIN2) 0:? 44e10808 00000027 pinctrl-single > pin 3 (PIN3) 0:? 44e1080c 00000027 pinctrl-single > pin 4 (PIN4) 0:? 44e10810 00000027 pinctrl-single > pin 5 (PIN5) 0:? 44e10814 00000027 pinctrl-single > pin 6 (PIN6) 0:? 44e10818 00000027 pinctrl-single > pin 7 (PIN7) 0:? 44e1081c 00000027 pinctrl-single > pin 8 (PIN8) 22:gpio-96-127 44e10820 00000027 pinctrl-single > pin 9 (PIN9) 23:gpio-96-127 44e10824 00000037 pinctrl-single > pin 10 (PIN10) 26:gpio-96-127 44e10828 00000037 pinctrl-single > pin 11 (PIN11) 27:gpio-96-127 44e1082c 00000037 pinctrl-single > pin 12 (PIN12) 0:? 44e10830 00000037 pinctrl-single > > pin 140 (PIN140) 0:? 44e10a30 00000028 pinctrl-single > pin 141 (PIN141) 13:gpio-64-95 44e10a34 00000020 pinctrl-single > > Reviewed-by: Drew Fustini Thanks for review and verify the change. Thanks, Hanna > > Thanks, > Drew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel