* [PATCHv2 1/1] net: ethernet: stmmac: simplify phy modes management for stm32
@ 2020-03-16 9:09 Christophe Roullier
2020-03-24 7:05 ` Christophe ROULLIER
2020-04-01 14:17 ` Alexandre Torgue
0 siblings, 2 replies; 5+ messages in thread
From: Christophe Roullier @ 2020-03-16 9:09 UTC (permalink / raw)
To: robh, davem, joabreu, mark.rutland, mcoquelin.stm32,
alexandre.torgue, peppe.cavallaro
Cc: devicetree, andrew, netdev, linux-kernel, linux-stm32,
christophe.roullier, linux-arm-kernel
No new feature, just to simplify stm32 part to be easier to use.
Add by default all Ethernet clocks in DT, and activate or not in function
of phy mode, clock frequency, if property "st,ext-phyclk" is set or not.
Keep backward compatibility
-----------------------------------------------------------------------
|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal | No 125Mhz |
| | | 25MHz | 50MHz | from PHY |
-----------------------------------------------------------------------
| MII | - | eth-ck | n/a | n/a |
| | | st,ext-phyclk | | |
-----------------------------------------------------------------------
| GMII | - | eth-ck | n/a | n/a |
| | | st,ext-phyclk | | |
-----------------------------------------------------------------------
| RGMII | - | eth-ck | n/a | eth-ck |
| | | st,ext-phyclk | |st,eth-clk-sel|
| | | | | or |
| | | | | st,ext-phyclk|
------------------------------------------------------------------------
| RMII | - | eth-ck | eth-ck | n/a |
| | | st,ext-phyclk | st,eth-ref-clk-sel | |
| | | | or st,ext-phyclk | |
------------------------------------------------------------------------
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 74 +++++++++++--------
1 file changed, 44 insertions(+), 30 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index b2dc99289687..5d4df4c5254e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -29,6 +29,11 @@
#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
+/* CLOCK feed to PHY*/
+#define ETH_CK_F_25M 25000000
+#define ETH_CK_F_50M 50000000
+#define ETH_CK_F_125M 125000000
+
/* Ethernet PHY interface selection in register SYSCFG Configuration
*------------------------------------------
* src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
@@ -58,33 +63,20 @@
*| | | 25MHz | 50MHz | |
* ---------------------------------------------------------------------------
*| MII | - | eth-ck | n/a | n/a |
- *| | | | | |
+ *| | | st,ext-phyclk | | |
* ---------------------------------------------------------------------------
*| GMII | - | eth-ck | n/a | n/a |
- *| | | | | |
+ *| | | st,ext-phyclk | | |
* ---------------------------------------------------------------------------
- *| RGMII | - | eth-ck | n/a | eth-ck (no pin) |
- *| | | | | st,eth-clk-sel |
+ *| RGMII | - | eth-ck | n/a | eth-ck |
+ *| | | st,ext-phyclk | | st,eth-clk-sel or|
+ *| | | | | st,ext-phyclk |
* ---------------------------------------------------------------------------
*| RMII | - | eth-ck | eth-ck | n/a |
- *| | | | st,eth-ref-clk-sel | |
+ *| | | st,ext-phyclk | st,eth-ref-clk-sel | |
+ *| | | | or st,ext-phyclk | |
* ---------------------------------------------------------------------------
*
- * BIT(17) : set this bit in RMII mode when you have PHY without crystal 50MHz
- * BIT(16) : set this bit in GMII/RGMII PHY when you do not want use 125Mhz
- * from PHY
- *-----------------------------------------------------
- * src | BIT(17) | BIT(16) |
- *-----------------------------------------------------
- * MII | n/a | n/a |
- *-----------------------------------------------------
- * GMII | n/a | st,eth-clk-sel |
- *-----------------------------------------------------
- * RGMII | n/a | st,eth-clk-sel |
- *-----------------------------------------------------
- * RMII | st,eth-ref-clk-sel | n/a |
- *-----------------------------------------------------
- *
*/
struct stm32_dwmac {
@@ -93,6 +85,8 @@ struct stm32_dwmac {
struct clk *clk_eth_ck;
struct clk *clk_ethstp;
struct clk *syscfg_clk;
+ int ext_phyclk;
+ int enable_eth_ck;
int eth_clk_sel_reg;
int eth_ref_clk_sel_reg;
int irq_pwr_wakeup;
@@ -155,14 +149,17 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
ret = clk_prepare_enable(dwmac->syscfg_clk);
if (ret)
return ret;
- ret = clk_prepare_enable(dwmac->clk_eth_ck);
- if (ret) {
- clk_disable_unprepare(dwmac->syscfg_clk);
- return ret;
+ if (dwmac->enable_eth_ck) {
+ ret = clk_prepare_enable(dwmac->clk_eth_ck);
+ if (ret) {
+ clk_disable_unprepare(dwmac->syscfg_clk);
+ return ret;
+ }
}
} else {
clk_disable_unprepare(dwmac->syscfg_clk);
- clk_disable_unprepare(dwmac->clk_eth_ck);
+ if (dwmac->enable_eth_ck)
+ clk_disable_unprepare(dwmac->clk_eth_ck);
}
return ret;
}
@@ -170,24 +167,34 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
{
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
- u32 reg = dwmac->mode_reg;
+ u32 reg = dwmac->mode_reg, clk_rate;
int val;
+ clk_rate = clk_get_rate(dwmac->clk_eth_ck);
+ dwmac->enable_eth_ck = false;
switch (plat_dat->interface) {
case PHY_INTERFACE_MODE_MII:
+ if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
+ dwmac->enable_eth_ck = true;
val = SYSCFG_PMCR_ETH_SEL_MII;
pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
break;
case PHY_INTERFACE_MODE_GMII:
val = SYSCFG_PMCR_ETH_SEL_GMII;
- if (dwmac->eth_clk_sel_reg)
+ if (clk_rate == ETH_CK_F_25M &&
+ (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
+ dwmac->enable_eth_ck = true;
val |= SYSCFG_PMCR_ETH_CLK_SEL;
+ }
pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
break;
case PHY_INTERFACE_MODE_RMII:
val = SYSCFG_PMCR_ETH_SEL_RMII;
- if (dwmac->eth_ref_clk_sel_reg)
+ if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) &&
+ (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
+ dwmac->enable_eth_ck = true;
val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
+ }
pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
break;
case PHY_INTERFACE_MODE_RGMII:
@@ -195,8 +202,11 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
val = SYSCFG_PMCR_ETH_SEL_RGMII;
- if (dwmac->eth_clk_sel_reg)
+ if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) &&
+ (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
+ dwmac->enable_eth_ck = true;
val |= SYSCFG_PMCR_ETH_CLK_SEL;
+ }
pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
break;
default:
@@ -294,6 +304,9 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
struct device_node *np = dev->of_node;
int err = 0;
+ /* Ethernet PHY have no crystal */
+ dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
+
/* Gigabit Ethernet 125MHz clock selection. */
dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
@@ -431,7 +444,8 @@ static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
clk_disable_unprepare(dwmac->clk_tx);
clk_disable_unprepare(dwmac->syscfg_clk);
- clk_disable_unprepare(dwmac->clk_eth_ck);
+ if (dwmac->enable_eth_ck)
+ clk_disable_unprepare(dwmac->clk_eth_ck);
return ret;
}
--
2.17.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCHv2 1/1] net: ethernet: stmmac: simplify phy modes management for stm32
2020-03-16 9:09 [PATCHv2 1/1] net: ethernet: stmmac: simplify phy modes management for stm32 Christophe Roullier
@ 2020-03-24 7:05 ` Christophe ROULLIER
2020-04-01 14:17 ` Alexandre Torgue
1 sibling, 0 replies; 5+ messages in thread
From: Christophe ROULLIER @ 2020-03-24 7:05 UTC (permalink / raw)
To: robh@kernel.org, davem@davemloft.net, joabreu@synopsys.com,
mark.rutland@arm.com, mcoquelin.stm32@gmail.com, Alexandre TORGUE,
Peppe CAVALLARO
Cc: devicetree@vger.kernel.org, andrew@lunn.ch,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org
Hi,
Gentle reminder
Thanks in advance.
Christophe.
On 16/03/2020 10:09, Christophe Roullier wrote:
> No new feature, just to simplify stm32 part to be easier to use.
> Add by default all Ethernet clocks in DT, and activate or not in function
> of phy mode, clock frequency, if property "st,ext-phyclk" is set or not.
> Keep backward compatibility
> -----------------------------------------------------------------------
> |PHY_MODE | Normal | PHY wo crystal| PHY wo crystal | No 125Mhz |
> | | | 25MHz | 50MHz | from PHY |
> -----------------------------------------------------------------------
> | MII | - | eth-ck | n/a | n/a |
> | | | st,ext-phyclk | | |
> -----------------------------------------------------------------------
> | GMII | - | eth-ck | n/a | n/a |
> | | | st,ext-phyclk | | |
> -----------------------------------------------------------------------
> | RGMII | - | eth-ck | n/a | eth-ck |
> | | | st,ext-phyclk | |st,eth-clk-sel|
> | | | | | or |
> | | | | | st,ext-phyclk|
> ------------------------------------------------------------------------
> | RMII | - | eth-ck | eth-ck | n/a |
> | | | st,ext-phyclk | st,eth-ref-clk-sel | |
> | | | | or st,ext-phyclk | |
> ------------------------------------------------------------------------
>
> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
>
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 74 +++++++++++--------
> 1 file changed, 44 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> index b2dc99289687..5d4df4c5254e 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> @@ -29,6 +29,11 @@
> #define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
> #define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
>
> +/* CLOCK feed to PHY*/
> +#define ETH_CK_F_25M 25000000
> +#define ETH_CK_F_50M 50000000
> +#define ETH_CK_F_125M 125000000
> +
> /* Ethernet PHY interface selection in register SYSCFG Configuration
> *------------------------------------------
> * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
> @@ -58,33 +63,20 @@
> *| | | 25MHz | 50MHz | |
> * ---------------------------------------------------------------------------
> *| MII | - | eth-ck | n/a | n/a |
> - *| | | | | |
> + *| | | st,ext-phyclk | | |
> * ---------------------------------------------------------------------------
> *| GMII | - | eth-ck | n/a | n/a |
> - *| | | | | |
> + *| | | st,ext-phyclk | | |
> * ---------------------------------------------------------------------------
> - *| RGMII | - | eth-ck | n/a | eth-ck (no pin) |
> - *| | | | | st,eth-clk-sel |
> + *| RGMII | - | eth-ck | n/a | eth-ck |
> + *| | | st,ext-phyclk | | st,eth-clk-sel or|
> + *| | | | | st,ext-phyclk |
> * ---------------------------------------------------------------------------
> *| RMII | - | eth-ck | eth-ck | n/a |
> - *| | | | st,eth-ref-clk-sel | |
> + *| | | st,ext-phyclk | st,eth-ref-clk-sel | |
> + *| | | | or st,ext-phyclk | |
> * ---------------------------------------------------------------------------
> *
> - * BIT(17) : set this bit in RMII mode when you have PHY without crystal 50MHz
> - * BIT(16) : set this bit in GMII/RGMII PHY when you do not want use 125Mhz
> - * from PHY
> - *-----------------------------------------------------
> - * src | BIT(17) | BIT(16) |
> - *-----------------------------------------------------
> - * MII | n/a | n/a |
> - *-----------------------------------------------------
> - * GMII | n/a | st,eth-clk-sel |
> - *-----------------------------------------------------
> - * RGMII | n/a | st,eth-clk-sel |
> - *-----------------------------------------------------
> - * RMII | st,eth-ref-clk-sel | n/a |
> - *-----------------------------------------------------
> - *
> */
>
> struct stm32_dwmac {
> @@ -93,6 +85,8 @@ struct stm32_dwmac {
> struct clk *clk_eth_ck;
> struct clk *clk_ethstp;
> struct clk *syscfg_clk;
> + int ext_phyclk;
> + int enable_eth_ck;
> int eth_clk_sel_reg;
> int eth_ref_clk_sel_reg;
> int irq_pwr_wakeup;
> @@ -155,14 +149,17 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
> ret = clk_prepare_enable(dwmac->syscfg_clk);
> if (ret)
> return ret;
> - ret = clk_prepare_enable(dwmac->clk_eth_ck);
> - if (ret) {
> - clk_disable_unprepare(dwmac->syscfg_clk);
> - return ret;
> + if (dwmac->enable_eth_ck) {
> + ret = clk_prepare_enable(dwmac->clk_eth_ck);
> + if (ret) {
> + clk_disable_unprepare(dwmac->syscfg_clk);
> + return ret;
> + }
> }
> } else {
> clk_disable_unprepare(dwmac->syscfg_clk);
> - clk_disable_unprepare(dwmac->clk_eth_ck);
> + if (dwmac->enable_eth_ck)
> + clk_disable_unprepare(dwmac->clk_eth_ck);
> }
> return ret;
> }
> @@ -170,24 +167,34 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
> static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
> {
> struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
> - u32 reg = dwmac->mode_reg;
> + u32 reg = dwmac->mode_reg, clk_rate;
> int val;
>
> + clk_rate = clk_get_rate(dwmac->clk_eth_ck);
> + dwmac->enable_eth_ck = false;
> switch (plat_dat->interface) {
> case PHY_INTERFACE_MODE_MII:
> + if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
> + dwmac->enable_eth_ck = true;
> val = SYSCFG_PMCR_ETH_SEL_MII;
> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
> break;
> case PHY_INTERFACE_MODE_GMII:
> val = SYSCFG_PMCR_ETH_SEL_GMII;
> - if (dwmac->eth_clk_sel_reg)
> + if (clk_rate == ETH_CK_F_25M &&
> + (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
> + dwmac->enable_eth_ck = true;
> val |= SYSCFG_PMCR_ETH_CLK_SEL;
> + }
> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
> break;
> case PHY_INTERFACE_MODE_RMII:
> val = SYSCFG_PMCR_ETH_SEL_RMII;
> - if (dwmac->eth_ref_clk_sel_reg)
> + if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) &&
> + (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
> + dwmac->enable_eth_ck = true;
> val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
> + }
> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
> break;
> case PHY_INTERFACE_MODE_RGMII:
> @@ -195,8 +202,11 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
> case PHY_INTERFACE_MODE_RGMII_RXID:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> val = SYSCFG_PMCR_ETH_SEL_RGMII;
> - if (dwmac->eth_clk_sel_reg)
> + if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) &&
> + (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
> + dwmac->enable_eth_ck = true;
> val |= SYSCFG_PMCR_ETH_CLK_SEL;
> + }
> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
> break;
> default:
> @@ -294,6 +304,9 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
> struct device_node *np = dev->of_node;
> int err = 0;
>
> + /* Ethernet PHY have no crystal */
> + dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
> +
> /* Gigabit Ethernet 125MHz clock selection. */
> dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
>
> @@ -431,7 +444,8 @@ static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
>
> clk_disable_unprepare(dwmac->clk_tx);
> clk_disable_unprepare(dwmac->syscfg_clk);
> - clk_disable_unprepare(dwmac->clk_eth_ck);
> + if (dwmac->enable_eth_ck)
> + clk_disable_unprepare(dwmac->clk_eth_ck);
>
> return ret;
> }
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCHv2 1/1] net: ethernet: stmmac: simplify phy modes management for stm32
2020-03-16 9:09 [PATCHv2 1/1] net: ethernet: stmmac: simplify phy modes management for stm32 Christophe Roullier
2020-03-24 7:05 ` Christophe ROULLIER
@ 2020-04-01 14:17 ` Alexandre Torgue
2020-04-14 15:10 ` Christophe ROULLIER
1 sibling, 1 reply; 5+ messages in thread
From: Alexandre Torgue @ 2020-04-01 14:17 UTC (permalink / raw)
To: Christophe Roullier, robh, davem, joabreu, mark.rutland,
mcoquelin.stm32, peppe.cavallaro
Cc: devicetree, andrew, netdev, linux-kernel, linux-stm32,
linux-arm-kernel
Hi Christophe
On 3/16/20 10:09 AM, Christophe Roullier wrote:
> No new feature, just to simplify stm32 part to be easier to use.
> Add by default all Ethernet clocks in DT, and activate or not in function
> of phy mode, clock frequency, if property "st,ext-phyclk" is set or not.
> Keep backward compatibility
> -----------------------------------------------------------------------
> |PHY_MODE | Normal | PHY wo crystal| PHY wo crystal | No 125Mhz |
> | | | 25MHz | 50MHz | from PHY |
> -----------------------------------------------------------------------
> | MII | - | eth-ck | n/a | n/a |
> | | | st,ext-phyclk | | |
> -----------------------------------------------------------------------
> | GMII | - | eth-ck | n/a | n/a |
> | | | st,ext-phyclk | | |
> -----------------------------------------------------------------------
> | RGMII | - | eth-ck | n/a | eth-ck |
> | | | st,ext-phyclk | |st,eth-clk-sel|
> | | | | | or |
> | | | | | st,ext-phyclk|
> ------------------------------------------------------------------------
> | RMII | - | eth-ck | eth-ck | n/a |
> | | | st,ext-phyclk | st,eth-ref-clk-sel | |
> | | | | or st,ext-phyclk | |
> ------------------------------------------------------------------------
>
> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
>
> ---
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
> .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 74 +++++++++++--------
> 1 file changed, 44 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> index b2dc99289687..5d4df4c5254e 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
> @@ -29,6 +29,11 @@
> #define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
> #define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
>
> +/* CLOCK feed to PHY*/
> +#define ETH_CK_F_25M 25000000
> +#define ETH_CK_F_50M 50000000
> +#define ETH_CK_F_125M 125000000
> +
> /* Ethernet PHY interface selection in register SYSCFG Configuration
> *------------------------------------------
> * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
> @@ -58,33 +63,20 @@
> *| | | 25MHz | 50MHz | |
> * ---------------------------------------------------------------------------
> *| MII | - | eth-ck | n/a | n/a |
> - *| | | | | |
> + *| | | st,ext-phyclk | | |
> * ---------------------------------------------------------------------------
> *| GMII | - | eth-ck | n/a | n/a |
> - *| | | | | |
> + *| | | st,ext-phyclk | | |
> * ---------------------------------------------------------------------------
> - *| RGMII | - | eth-ck | n/a | eth-ck (no pin) |
> - *| | | | | st,eth-clk-sel |
> + *| RGMII | - | eth-ck | n/a | eth-ck |
> + *| | | st,ext-phyclk | | st,eth-clk-sel or|
> + *| | | | | st,ext-phyclk |
> * ---------------------------------------------------------------------------
> *| RMII | - | eth-ck | eth-ck | n/a |
> - *| | | | st,eth-ref-clk-sel | |
> + *| | | st,ext-phyclk | st,eth-ref-clk-sel | |
> + *| | | | or st,ext-phyclk | |
> * ---------------------------------------------------------------------------
> *
> - * BIT(17) : set this bit in RMII mode when you have PHY without crystal 50MHz
> - * BIT(16) : set this bit in GMII/RGMII PHY when you do not want use 125Mhz
> - * from PHY
> - *-----------------------------------------------------
> - * src | BIT(17) | BIT(16) |
> - *-----------------------------------------------------
> - * MII | n/a | n/a |
> - *-----------------------------------------------------
> - * GMII | n/a | st,eth-clk-sel |
> - *-----------------------------------------------------
> - * RGMII | n/a | st,eth-clk-sel |
> - *-----------------------------------------------------
> - * RMII | st,eth-ref-clk-sel | n/a |
> - *-----------------------------------------------------
> - *
> */
>
> struct stm32_dwmac {
> @@ -93,6 +85,8 @@ struct stm32_dwmac {
> struct clk *clk_eth_ck;
> struct clk *clk_ethstp;
> struct clk *syscfg_clk;
> + int ext_phyclk;
> + int enable_eth_ck;
> int eth_clk_sel_reg;
> int eth_ref_clk_sel_reg;
> int irq_pwr_wakeup;
> @@ -155,14 +149,17 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
> ret = clk_prepare_enable(dwmac->syscfg_clk);
> if (ret)
> return ret;
> - ret = clk_prepare_enable(dwmac->clk_eth_ck);
> - if (ret) {
> - clk_disable_unprepare(dwmac->syscfg_clk);
> - return ret;
> + if (dwmac->enable_eth_ck) {
> + ret = clk_prepare_enable(dwmac->clk_eth_ck);
> + if (ret) {
> + clk_disable_unprepare(dwmac->syscfg_clk);
> + return ret;
> + }
> }
> } else {
> clk_disable_unprepare(dwmac->syscfg_clk);
> - clk_disable_unprepare(dwmac->clk_eth_ck);
> + if (dwmac->enable_eth_ck)
> + clk_disable_unprepare(dwmac->clk_eth_ck);
> }
> return ret;
> }
> @@ -170,24 +167,34 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
> static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
> {
> struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
> - u32 reg = dwmac->mode_reg;
> + u32 reg = dwmac->mode_reg, clk_rate;
> int val;
>
> + clk_rate = clk_get_rate(dwmac->clk_eth_ck);
> + dwmac->enable_eth_ck = false;
> switch (plat_dat->interface) {
> case PHY_INTERFACE_MODE_MII:
> + if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
> + dwmac->enable_eth_ck = true;
> val = SYSCFG_PMCR_ETH_SEL_MII;
> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
> break;
> case PHY_INTERFACE_MODE_GMII:
> val = SYSCFG_PMCR_ETH_SEL_GMII;
> - if (dwmac->eth_clk_sel_reg)
> + if (clk_rate == ETH_CK_F_25M &&
> + (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
> + dwmac->enable_eth_ck = true;
> val |= SYSCFG_PMCR_ETH_CLK_SEL;
> + }
> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
> break;
> case PHY_INTERFACE_MODE_RMII:
> val = SYSCFG_PMCR_ETH_SEL_RMII;
> - if (dwmac->eth_ref_clk_sel_reg)
> + if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) &&
> + (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
> + dwmac->enable_eth_ck = true;
> val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
> + }
> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
> break;
> case PHY_INTERFACE_MODE_RGMII:
> @@ -195,8 +202,11 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
> case PHY_INTERFACE_MODE_RGMII_RXID:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> val = SYSCFG_PMCR_ETH_SEL_RGMII;
> - if (dwmac->eth_clk_sel_reg)
> + if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) &&
> + (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
> + dwmac->enable_eth_ck = true;
> val |= SYSCFG_PMCR_ETH_CLK_SEL;
> + }
> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
> break;
> default:
> @@ -294,6 +304,9 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
> struct device_node *np = dev->of_node;
> int err = 0;
>
> + /* Ethernet PHY have no crystal */
> + dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
> +
> /* Gigabit Ethernet 125MHz clock selection. */
> dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
>
> @@ -431,7 +444,8 @@ static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
>
> clk_disable_unprepare(dwmac->clk_tx);
> clk_disable_unprepare(dwmac->syscfg_clk);
> - clk_disable_unprepare(dwmac->clk_eth_ck);
> + if (dwmac->enable_eth_ck)
> + clk_disable_unprepare(dwmac->clk_eth_ck);
>
> return ret;
> }
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCHv2 1/1] net: ethernet: stmmac: simplify phy modes management for stm32
2020-04-01 14:17 ` Alexandre Torgue
@ 2020-04-14 15:10 ` Christophe ROULLIER
2020-04-14 15:14 ` Andrew Lunn
0 siblings, 1 reply; 5+ messages in thread
From: Christophe ROULLIER @ 2020-04-14 15:10 UTC (permalink / raw)
To: Alexandre TORGUE, robh@kernel.org, davem@davemloft.net,
joabreu@synopsys.com, mark.rutland@arm.com,
mcoquelin.stm32@gmail.com, Peppe CAVALLARO
Cc: devicetree@vger.kernel.org, andrew@lunn.ch,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org
Hi,
Gentle reminder
Thanks,
Christophe.
On 01/04/2020 16:17, Alexandre Torgue wrote:
> Hi Christophe
>
> On 3/16/20 10:09 AM, Christophe Roullier wrote:
>> No new feature, just to simplify stm32 part to be easier to use.
>> Add by default all Ethernet clocks in DT, and activate or not in
>> function
>> of phy mode, clock frequency, if property "st,ext-phyclk" is set or not.
>> Keep backward compatibility
>> -----------------------------------------------------------------------
>> |PHY_MODE | Normal | PHY wo crystal| PHY wo crystal | No 125Mhz |
>> | | | 25MHz | 50MHz | from PHY |
>> -----------------------------------------------------------------------
>> | MII | - | eth-ck | n/a | n/a |
>> | | | st,ext-phyclk | | |
>> -----------------------------------------------------------------------
>> | GMII | - | eth-ck | n/a | n/a |
>> | | | st,ext-phyclk | | |
>> -----------------------------------------------------------------------
>> | RGMII | - | eth-ck | n/a | eth-ck |
>> | | | st,ext-phyclk | |st,eth-clk-sel|
>> | | | | | or |
>> | | | | | st,ext-phyclk|
>> ------------------------------------------------------------------------
>> | RMII | - | eth-ck | eth-ck | n/a |
>> | | | st,ext-phyclk | st,eth-ref-clk-sel | |
>> | | | | or st,ext-phyclk | |
>> ------------------------------------------------------------------------
>>
>> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
>>
>> ---
>
> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
>
>
>> .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 74 +++++++++++--------
>> 1 file changed, 44 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
>> b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
>> index b2dc99289687..5d4df4c5254e 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
>> @@ -29,6 +29,11 @@
>> #define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
>> #define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
>> +/* CLOCK feed to PHY*/
>> +#define ETH_CK_F_25M 25000000
>> +#define ETH_CK_F_50M 50000000
>> +#define ETH_CK_F_125M 125000000
>> +
>> /* Ethernet PHY interface selection in register SYSCFG Configuration
>> *------------------------------------------
>> * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
>> @@ -58,33 +63,20 @@
>> *| | | 25MHz | 50MHz
>> | |
>> *
>> ---------------------------------------------------------------------------
>> *| MII | - | eth-ck | n/a |
>> n/a |
>> - *| | | | | |
>> + *| | | st,ext-phyclk | | |
>> *
>> ---------------------------------------------------------------------------
>> *| GMII | - | eth-ck | n/a |
>> n/a |
>> - *| | | | | |
>> + *| | | st,ext-phyclk | | |
>> *
>> ---------------------------------------------------------------------------
>> - *| RGMII | - | eth-ck | n/a | eth-ck
>> (no pin) |
>> - *| | | | |
>> st,eth-clk-sel |
>> + *| RGMII | - | eth-ck | n/a |
>> eth-ck |
>> + *| | | st,ext-phyclk | |
>> st,eth-clk-sel or|
>> + *| | | | |
>> st,ext-phyclk |
>> *
>> ---------------------------------------------------------------------------
>> *| RMII | - | eth-ck | eth-ck |
>> n/a |
>> - *| | | | st,eth-ref-clk-sel | |
>> + *| | | st,ext-phyclk | st,eth-ref-clk-sel
>> | |
>> + *| | | | or st,ext-phyclk | |
>> *
>> ---------------------------------------------------------------------------
>> *
>> - * BIT(17) : set this bit in RMII mode when you have PHY without
>> crystal 50MHz
>> - * BIT(16) : set this bit in GMII/RGMII PHY when you do not want use
>> 125Mhz
>> - * from PHY
>> - *-----------------------------------------------------
>> - * src | BIT(17) | BIT(16) |
>> - *-----------------------------------------------------
>> - * MII | n/a | n/a |
>> - *-----------------------------------------------------
>> - * GMII | n/a | st,eth-clk-sel |
>> - *-----------------------------------------------------
>> - * RGMII | n/a | st,eth-clk-sel |
>> - *-----------------------------------------------------
>> - * RMII | st,eth-ref-clk-sel | n/a |
>> - *-----------------------------------------------------
>> - *
>> */
>> struct stm32_dwmac {
>> @@ -93,6 +85,8 @@ struct stm32_dwmac {
>> struct clk *clk_eth_ck;
>> struct clk *clk_ethstp;
>> struct clk *syscfg_clk;
>> + int ext_phyclk;
>> + int enable_eth_ck;
>> int eth_clk_sel_reg;
>> int eth_ref_clk_sel_reg;
>> int irq_pwr_wakeup;
>> @@ -155,14 +149,17 @@ static int stm32mp1_clk_prepare(struct
>> stm32_dwmac *dwmac, bool prepare)
>> ret = clk_prepare_enable(dwmac->syscfg_clk);
>> if (ret)
>> return ret;
>> - ret = clk_prepare_enable(dwmac->clk_eth_ck);
>> - if (ret) {
>> - clk_disable_unprepare(dwmac->syscfg_clk);
>> - return ret;
>> + if (dwmac->enable_eth_ck) {
>> + ret = clk_prepare_enable(dwmac->clk_eth_ck);
>> + if (ret) {
>> + clk_disable_unprepare(dwmac->syscfg_clk);
>> + return ret;
>> + }
>> }
>> } else {
>> clk_disable_unprepare(dwmac->syscfg_clk);
>> - clk_disable_unprepare(dwmac->clk_eth_ck);
>> + if (dwmac->enable_eth_ck)
>> + clk_disable_unprepare(dwmac->clk_eth_ck);
>> }
>> return ret;
>> }
>> @@ -170,24 +167,34 @@ static int stm32mp1_clk_prepare(struct
>> stm32_dwmac *dwmac, bool prepare)
>> static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
>> {
>> struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
>> - u32 reg = dwmac->mode_reg;
>> + u32 reg = dwmac->mode_reg, clk_rate;
>> int val;
>> + clk_rate = clk_get_rate(dwmac->clk_eth_ck);
>> + dwmac->enable_eth_ck = false;
>> switch (plat_dat->interface) {
>> case PHY_INTERFACE_MODE_MII:
>> + if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
>> + dwmac->enable_eth_ck = true;
>> val = SYSCFG_PMCR_ETH_SEL_MII;
>> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
>> break;
>> case PHY_INTERFACE_MODE_GMII:
>> val = SYSCFG_PMCR_ETH_SEL_GMII;
>> - if (dwmac->eth_clk_sel_reg)
>> + if (clk_rate == ETH_CK_F_25M &&
>> + (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
>> + dwmac->enable_eth_ck = true;
>> val |= SYSCFG_PMCR_ETH_CLK_SEL;
>> + }
>> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
>> break;
>> case PHY_INTERFACE_MODE_RMII:
>> val = SYSCFG_PMCR_ETH_SEL_RMII;
>> - if (dwmac->eth_ref_clk_sel_reg)
>> + if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) &&
>> + (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
>> + dwmac->enable_eth_ck = true;
>> val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
>> + }
>> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
>> break;
>> case PHY_INTERFACE_MODE_RGMII:
>> @@ -195,8 +202,11 @@ static int stm32mp1_set_mode(struct
>> plat_stmmacenet_data *plat_dat)
>> case PHY_INTERFACE_MODE_RGMII_RXID:
>> case PHY_INTERFACE_MODE_RGMII_TXID:
>> val = SYSCFG_PMCR_ETH_SEL_RGMII;
>> - if (dwmac->eth_clk_sel_reg)
>> + if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) &&
>> + (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
>> + dwmac->enable_eth_ck = true;
>> val |= SYSCFG_PMCR_ETH_CLK_SEL;
>> + }
>> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
>> break;
>> default:
>> @@ -294,6 +304,9 @@ static int stm32mp1_parse_data(struct stm32_dwmac
>> *dwmac,
>> struct device_node *np = dev->of_node;
>> int err = 0;
>> + /* Ethernet PHY have no crystal */
>> + dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
>> +
>> /* Gigabit Ethernet 125MHz clock selection. */
>> dwmac->eth_clk_sel_reg = of_property_read_bool(np,
>> "st,eth-clk-sel");
>> @@ -431,7 +444,8 @@ static int stm32mp1_suspend(struct stm32_dwmac
>> *dwmac)
>> clk_disable_unprepare(dwmac->clk_tx);
>> clk_disable_unprepare(dwmac->syscfg_clk);
>> - clk_disable_unprepare(dwmac->clk_eth_ck);
>> + if (dwmac->enable_eth_ck)
>> + clk_disable_unprepare(dwmac->clk_eth_ck);
>> return ret;
>> }
>>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCHv2 1/1] net: ethernet: stmmac: simplify phy modes management for stm32
2020-04-14 15:10 ` Christophe ROULLIER
@ 2020-04-14 15:14 ` Andrew Lunn
0 siblings, 0 replies; 5+ messages in thread
From: Andrew Lunn @ 2020-04-14 15:14 UTC (permalink / raw)
To: Christophe ROULLIER
Cc: mark.rutland@arm.com, robh@kernel.org, Alexandre TORGUE,
devicetree@vger.kernel.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com, joabreu@synopsys.com,
mcoquelin.stm32@gmail.com, Peppe CAVALLARO, davem@davemloft.net,
linux-arm-kernel@lists.infradead.org
On Tue, Apr 14, 2020 at 03:10:26PM +0000, Christophe ROULLIER wrote:
> Hi,
>
> Gentle reminder
Hi Christophe
You are more likely to have success if you repost.
Andrew
_______________________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-14 15:15 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2020-03-16 9:09 [PATCHv2 1/1] net: ethernet: stmmac: simplify phy modes management for stm32 Christophe Roullier
2020-03-24 7:05 ` Christophe ROULLIER
2020-04-01 14:17 ` Alexandre Torgue
2020-04-14 15:10 ` Christophe ROULLIER
2020-04-14 15:14 ` Andrew Lunn
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