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Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by GV4PR04MB11975.eurprd04.prod.outlook.com (2603:10a6:150:2ec::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.31; Mon, 23 Mar 2026 08:17:33 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::4609:64af:8a4b:fd64]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::4609:64af:8a4b:fd64%3]) with mapi id 15.20.9723.022; Mon, 23 Mar 2026 08:17:25 +0000 Message-ID: Date: Mon, 23 Mar 2026 16:18:55 +0800 User-Agent: Mozilla Thunderbird Subject: Re: i.MX8MP: Fix HDMI LCDIF FIFO underruns To: =?UTF-8?Q?Krzysztof_Ha=C5=82asa?= , Maxime Ripard Cc: Marco Felsch , Marek Vasut , Stefan Agner , Simona Vetter , imx@lists.linux.dev, Fabio Estevam , Pengutronix Kernel Team , Maarten Lankhorst , Sascha Hauer , Frank Li , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Thomas Zimmermann , David Airlie , linux-arm-kernel@lists.infradead.org, Lucas Stach References: <32317022-3c44-4ead-9e2d-04caa12b28cb@nabladev.com> <20260320-amiable-hairy-bullfinch-28bfda@houat> From: Liu Ying Content-Language: en-US In-Reply-To: Content-Type: text/plain; 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I.e., the display may freeze > at weston start and/or shutdown time, but otherwise works: If you may use a display mode with low resolution, say 640x480p60, and the issue still happens, then I bet it's not related to the panic threshold settings, but more likely related to KMS detail control seqeunce. This reminds me that Lucas had a patch series[1] to try to fix the sequence, but it seems that it didn't fix i.MX93 LCDIF according to [2] hence no landing. [1] https://lore.kernel.org/all/20230928113629.103188-1-l.stach@pengutronix.de/#t [2] https://lore.kernel.org/all/AM7PR04MB7046FF021B8BA46EFB758BA098CFA@AM7PR04MB7046.eurprd04.prod.outlook.com/ Cc'ing Lucas. > > v6.19 (frozen screen while starting weston, same display, the patch > applied): > 32FC6000: 2 2 2 2 > 32FC6010: 80000000 8700F00 12800B0 480008 > 32FC6020: A0058 1000007 0 > 32FC6030: 1 1 > 32FC6200: 8700F00 223C00 EF000000 > 32FC6210: 0 89000000 1 > 32FC6220: 0 0 0 0 > 32FC6230: 0 0 AB0155 > > OTOH NXP's 6.6.23 works all the time: > NCP v6.6.23 (a different i.MX8MP): > 32FC6000: A A A A > 32FC6010: 80000000 8700F00 12800B0 480008 > 32FC6020: A0058 10005 0 > 32FC6030: 1 1 > 32FC6200: 8700F00 A23C00 97C00000 > 32FC6210: 0 89000000 1 > 32FC6220: 0 0 0 0 > 32FC6230: 0 0 AB0155 A newer downstream kernel with newer kernel version dumps reg@32FC6230 as 0x01000180 instead of 0xAB0155. Note that this downstream kernel sets lcdif3 thresholds in DT: &lcdif3 { status = "okay"; thres-low = <1 2>; /* (FIFO * 1 / 2) */ thres-high = <3 4>; /* (FIFO * 3 / 4) */ }; I didn't tune/determine the threshold settings for downstream kernel, so what could I say? Maybe, align upstream kernel with downstream kernel. > > 32FC600x 2 vs. A is pixel clock inversion. > 32FC6208 is config P_SIZE, T_SIZE + pitch. > > More tests after weekend. -- Regards, Liu Ying