From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E469C3DA4A for ; Thu, 1 Aug 2024 11:42:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fAeZbCb7HEM4IRNiB1tGJVhRjUYfu48sF6D4/7YhuQ8=; b=VjH038y7EtnUVuUltjQ1JOV+2k cO/D769SYg3PHblpzOrqpHMC9v0L6yZSPgu6Ov/eyS6XWA06SlYJwSQElLwjbl0mVJo338vMrDaXd x7vIFbCTCWvWnC2ErZHIdMEilgQGc2uCBmkDuPGE7RjT0AVTVAOvSfINmH/TtvLUR3sFVxqXVgV/R Weh9tB98ibJqnhLEbZ86+g9BlX44TlBGJP3I32GpD6M30zur0Ujpz0J6ywNk0QWobRZM1WI3J/frA gM4lwUDW1+MveHCFxJ8nqNrZPzznIyKp7OdUKAkgURzcKZBx3IQUZjSjk0ZJfuMOtHNe+qTl0mC9e ofh+oKVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZUCd-00000004x5b-15Ru; Thu, 01 Aug 2024 11:42:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZUC9-00000004x34-3w2S for linux-arm-kernel@lists.infradead.org; Thu, 01 Aug 2024 11:42:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BE792367; Thu, 1 Aug 2024 04:42:33 -0700 (PDT) Received: from [10.163.56.112] (unknown [10.163.56.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60F583F5A1; Thu, 1 Aug 2024 04:42:06 -0700 (PDT) Message-ID: Date: Thu, 1 Aug 2024 17:12:03 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] arm64: cputype: Add Cortex-X1C definitions To: Mark Rutland , linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, james.morse@arm.com, will@kernel.org References: <20240801101803.1982459-1-mark.rutland@arm.com> <20240801101803.1982459-2-mark.rutland@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20240801101803.1982459-2-mark.rutland@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240801_044210_065310_DE183918 X-CRM114-Status: GOOD ( 13.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/1/24 15:48, Mark Rutland wrote: > Add cputype definitions for Cortex-X1C. These will be used for errata > detection in subsequent patches. > > These values can be found in the Cortex-X1C TRM: > > https://developer.arm.com/documentation/101968/0002/ > > ... in section B2.107 ("MIDR_EL1, Main ID Register, EL1"). > > Signed-off-by: Mark Rutland > Cc: Catalin Marinas > Cc: James Morse > Cc: Will Deacon > --- > arch/arm64/include/asm/cputype.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 1cb0704c6163f..5dc68ace305e5 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -86,6 +86,7 @@ > #define ARM_CPU_PART_CORTEX_X2 0xD48 > #define ARM_CPU_PART_NEOVERSE_N2 0xD49 > #define ARM_CPU_PART_CORTEX_A78C 0xD4B > +#define ARM_CPU_PART_CORTEX_X1C 0xD4C > #define ARM_CPU_PART_CORTEX_X3 0xD4E > #define ARM_CPU_PART_NEOVERSE_V2 0xD4F > #define ARM_CPU_PART_CORTEX_A720 0xD81 > @@ -165,6 +166,7 @@ > #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) > #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) > #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) > +#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) > #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) > #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) > #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) The CPU part number 0xD4C checks out in the mentioned document above. Reviewed-by: Anshuman Khandual