From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D497C433E2 for ; Wed, 2 Sep 2020 23:08:43 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18EE020767 for ; Wed, 2 Sep 2020 23:08:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Yq9lHQu/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 18EE020767 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Mime-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XrlmsFBvgLhoGVuQpmCnY/9N0PEt05ThVXlwV4kmbgA=; b=Yq9lHQu/uF5ZdT5vtggRGwuSd KKCYhCn9zfM8cew54XNtfpZs9INaA7udHlt3nPn7Ky/ml8WofbzeoXirXw/dW49oZxZVkwLhOw4n4 Aee2sih5blbJ8I/s64ddwvXpRRaEGoiTQQPPvwBJSk7JmxTzlgceEjvvv2w180CVUDB92eFY0dXEo 9I1lFt8dwZTgQgXgGMRtO80K7ccT8uwEW3qnDL7ANHkblzPZPzHbD5f+Q5Wc3wD5LTOoAx75MXozI jRVBv7IUuglBimAsPCTAD/NInZFgan43zpJy/rNwC4SfsEbzqxMk+XnA91XFlCAay2flwJSGriwjQ i8LLymjXA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kDbqg-0001EF-Ju; Wed, 02 Sep 2020 23:07:26 +0000 Received: from kernel.crashing.org ([76.164.61.194]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kDbqe-0001Dn-4z for linux-arm-kernel@lists.infradead.org; Wed, 02 Sep 2020 23:07:24 +0000 Received: from localhost (gate.crashing.org [63.228.1.57]) (authenticated bits=0) by kernel.crashing.org (8.14.7/8.14.7) with ESMTP id 082N72VH005449 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 2 Sep 2020 18:07:06 -0500 Message-ID: Subject: Re: [PATCH] arm64: Enable PCI write-combine resources under sysfs From: Benjamin Herrenschmidt To: Lorenzo Pieralisi , Clint Sbisa Date: Thu, 03 Sep 2020 09:07:00 +1000 In-Reply-To: <20200902164702.GA30611@e121166-lin.cambridge.arm.com> References: <20200831151827.pumm2p54fyj7fz5s@amazon.com> <20200902113207.GA27676@e121166-lin.cambridge.arm.com> <20200902142922.xc4x6m33unkzewuh@amazon.com> <20200902164702.GA30611@e121166-lin.cambridge.arm.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200902_190724_324362_67D149BD X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, will@kernel.org, Bjorn Helgaas , linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2020-09-02 at 17:47 +0100, Lorenzo Pieralisi wrote: > Yes I do and I expressed them. > > The first concern is the WC ambiguity on non-x86 systems, it looks > like write combinining means everything and nothing at the same time > on != x86 arches. > > On x86 prefetchable BAR == WC mapping (still conditional on arch > features ie PAT, not a blanket enable). On ARM64 WC mapping currently > corresponds to normal NC memory and the PCIe specs allow read > side-effects BAR to be marked as prefetchable, I need to force PCI > sig > to remove the section I mentioned from the specifications because > there > is NO way it can be detected if a prefetchable BAR maps to read > side-effects memory. Im not sure I understand your sentence. It's been a long accepted rule in PCI land that "prefetchable" BARs means "no side effects" and in fact allows much more than just prefetching :-) > A kernel device driver would (hopefully) know, sysfs code that just > checks the prefetchable attribute and exports resource_WC does not. > > As I mentioned, if the mapping is done in a device specific driver it > can be vetted and there are not many drivers mapping BARs as > ioremap_wc(). It's been what other architectures have been doing for mroe than a decade without significant issues... I don't think you should worry too much about this. Cheers, Ben. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel