From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBCB5C433F5 for ; Tue, 31 May 2022 16:27:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q40Pt6QYOYMhV1pv2BcJ30Ppfcm2CM/BZFkZqmtzP1M=; b=wkPOjuu8QpsAge dggygsU5xK+YjnLHSoPS1MpFHvU9toaFHDPeAzLqUPpTlcRjQmRyicCTAC2+WduvWqIKIQPIyaGID EV+VQCPPh3xot2ywDlihSfDRzg5PCoaX1yuMonEouBDnhdRrObPSIxfjHCF1VfJk1pPo+I9MqBGYq Irzd3MZ6OimhKqp9M7Av8UnoCMLevX1LxYqM5k5T5Kux+AuR6WqMRjNUrmm8Tm4Uss218AfDCjmcK JvEvf8Kvt9cbd5Q3YdWL8JOhbWQuSOmIP7+mib/Cpiedf4nCk5a0LGVDp0tZ6fpFJJfXcu/fgUZj9 PV3+cpRK/WUJzRqV4lqg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nw4hP-00BmWg-7P; Tue, 31 May 2022 16:26:27 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nw4hL-00BmUM-4F for linux-arm-kernel@lists.infradead.org; Tue, 31 May 2022 16:26:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 484C023A; Tue, 31 May 2022 09:26:21 -0700 (PDT) Received: from [10.57.81.38] (unknown [10.57.81.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9E8023F73D; Tue, 31 May 2022 09:26:19 -0700 (PDT) Message-ID: Date: Tue, 31 May 2022 17:26:14 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior Content-Language: en-GB To: Will Deacon , Konrad Dybcio Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jamipkettunen@somainline.org, iommu@lists.linux-foundation.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, linux-arm-kernel@lists.infradead.org References: <20220527212901.29268-1-konrad.dybcio@somainline.org> <20220527212901.29268-3-konrad.dybcio@somainline.org> <20220531155559.GB25502@willie-the-truck> From: Robin Murphy In-Reply-To: <20220531155559.GB25502@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220531_092623_266889_EC9E8B81 X-CRM114-Status: GOOD ( 19.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-05-31 16:55, Will Deacon wrote: > On Fri, May 27, 2022 at 11:28:57PM +0200, Konrad Dybcio wrote: >> From: AngeloGioacchino Del Regno >> >> As also stated in the arm-smmu driver, we must write the TCR before >> writing the TTBRs, since the TCR determines the access behavior of >> some fields. > > Where is this stated in the arm-smmu driver? In arm_smmu_write_context_bank() - IIRC it's mostly about the case where if you write a 16-bit ASID to TTBR before setting TCR2.AS you might end up losing the top 8 bits of it. However, in the context of a pantomime where we just have to pretend to program the "hardware" the way the firmware has already programmed it (on pain of getting randomly reset if we look at it wrong), I can't imagine it really matters. Robin. >> Signed-off-by: AngeloGioacchino Del Regno >> Signed-off-by: Marijn Suijten >> Signed-off-by: Konrad Dybcio >> --- >> drivers/iommu/arm/arm-smmu/qcom_iommu.c | 12 ++++++------ >> 1 file changed, 6 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> index 1728d4d7fe25..75f353866c40 100644 >> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> @@ -273,18 +273,18 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, >> ctx->secure_init = true; >> } >> >> - /* TTBRs */ >> - iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, >> - pgtbl_cfg.arm_lpae_s1_cfg.ttbr | >> - FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); >> - iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); >> - >> /* TCR */ >> iommu_writel(ctx, ARM_SMMU_CB_TCR2, >> arm_smmu_lpae_tcr2(&pgtbl_cfg)); >> iommu_writel(ctx, ARM_SMMU_CB_TCR, >> arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE); >> >> + /* TTBRs */ >> + iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, >> + pgtbl_cfg.arm_lpae_s1_cfg.ttbr | >> + FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); >> + iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); > > I'd have thought that SCTLR.M would be clear here, so it shouldn't matter > what order we write these in. > > Will > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel